
W78LE365
ADDRESS BUS
Bit Length
Selectable
P4xAH
EQUAL
P4.x
WR_CS
P4 REGISTER
P4.x
READ
WRITE
DATA I/O
RD_CS
RD/WR_CS
P4xCMP0
P4xFUN0
P4xFUN1
P4xCSINV
P4.x INPUT DATA BUS
REGISTER
PIN
6.7 Pulse Width Modulated Outputs (PWM)
There are five pulse width modulated output channels to generate pulses of programmable length and
interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for
the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts
modular 255 (0
254). The value of the 8-bit counter compared to the contents of five registers:
PWM0, PWM1, PWM2, PWM3 and PWM4. Provided the contents of either these registers is greater
than the counter value, the corresponding PWM0, PWM1, PWM2, PWM3 or PWM4 output is set
HIGH. If the contents of these registers are equal to, or less than the counter value, the output will be
LOW. The pulse-width-ratio is defined by the contents of the registers PWM0, PWM1, PWM2, PWM3
and PWM4. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of
1/255. ENPWM0, ENPWM1, ENPWM2, ENPWM3 and ENPWM4 bit will enable or disable PWM
output.
Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be
proportional to the contents of PWM0/1/2/3/4. The repetition frequency
output is given by:
f
f
pwm
, at the PWM0/1/2/3/4
pwm
f
255
)
1
×
2
×
+
=
PWMP
osc
Prescaler division factor = PWM + 1
PWMn high/low ratio of
(PWMn)
-
255
PWMn)
(
PWMn
=
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