
W79E804A/803A/802A
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Continued
BIT
NAME
FUNCTION
2
OE1
Output enable:
1: The comparator output is connected to the CMP1 pin if the comparator is
enabled (CE1 = 1). This output is asynchronous to the CPU clock.
Comparator output:
Synchronized to the CPU clock to allow reading by software. Cleared when the
comparator is disabled (CE1 = 0).
Comparator interrupt flag:
This bit is set by hardware whenever the comparator output CO1 changes state.
This bit will cause a hardware interrupt if enabled and of sufficient priority.
Cleared by software and when the comparator is disabled (CE1 = 0).
1
CO1
0
CMF1
COMPARATOR 2 CONTROL REGISTER
Bit:
7
6
5
4
3
2
1
0
-
-
CE2
CP2
CN2
OE2
CO2
CMF2
Mnemonic: CMP2
Address: ADh
BIT
7
6
NAME
FUNCTION
-
-
Reserved.
Reserved.
Comparator enable:
0: Disable Comparator.
1: Enabled Comparator. Comparator output need wait stable 10 us after CE2 is
first set.
Comparator positive input select:
0: CIN2A is selected as the positive comparator input.
1: CIN2B is selected as the positive comparator input.
Comparator negative input select:
0: The comparator reference pin CMPREF is selected as the negative
comparator input.
1: The internal comparator reference Vref is selected as the negative comparator
input.
Output enable:
1: The comparator output is connected to the CMP2 pin if the comparator is
enabled (CE2 = 1). This output is asynchronous to the CPU clock.
Comparator output:
Synchronized to the CPU clock to allow reading by software. Cleared when the
comparator is disabled (CE2 = 0).
Comparator interrupt flag:
This bit is set by hardware whenever the comparator output CO2 changes state.
This bit will cause a hardware interrupt if enabled and of sufficient priority.
Cleared by software and when the comparator is disabled (CE2 = 0).
5
CE2
4
CP2
3
CN2
2
OE2
1
CO2
0
CMF2