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參數資料
| 型號： | W83195R-08 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | XO, clock |
| 英文描述： | 150MHZ 4-DIMM Clock(頻率為150MHZ、3-DIMM 時鐘) |
| 中文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | SSOP-56 |
| 文件頁數： | 6/18頁 |
| 文件大小： | 230K |
| 代理商： | W83195R-08 |
W83195R-08
PRELIMINARY
Publication Release Date: Mar. 1999
Revision 0.30
- 6 -
8.0 FUNTION DESCRIPTION
8.1 POWER MANAGEMENT FUNCTIONS
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO
s
to stabilize prior to enabling clock outputs to
assure correct pulse widths. When MODE=0, pins 3 and 47 are inputs (PCI_STOP#), (CPU_STOP#),
when MODE=1, these functions are not available. A particular clock can be enabled as both the 2-
wire serial control interface and one of these pins indicate that it should be enable.
The W83195R-08 may be disabled in the low state according to the following table in order to reduce
power consumption. All clocks are stopped in the low state, but maintain a valid high period on
transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP#
PCI_STOP#
CPUCLK[1:2]
IOAPIC0 &
SDRAM [0:15]
PCI
OTHER CLKs
XTAL & VCOs
0
0
LOW
LOW
RUNNING
RUNNING
0
1
LOW
RUNNING
RUNNING
RUNNING
1
0
RUNNING
LOW
RUNNING
RUNNING
1
1
RUNNING
RUNNING
RUNNING
RUNNING
8.2 2-WIRE I
2
C CONTROL INTERFACE
The clock generator is a slave I
2
C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83195R-08 initializes with default register settings. Use of the 2-wire control interface is then
optional.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address and a write command bit
[1101 0010], command code checking [0000 0000], and byte count checking. After successful
reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip.
Controller can start to write to internal I
2
C registers after the string of data. The sequence order is as
follows:
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| W83196G-718 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VIA BUFFER CHIP (4 X DDR or 2 X DDR + 3 X SDRAM) |
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