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參數(shù)資料
| 型號： | W83626F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | LPC-to-ISA Bridge |
| 中文描述： | 線性預測到的ISA橋 |
| 文件頁數(shù)： | 8/34頁 |
| 文件大小： | 343K |
| 代理商： | W83626F |
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LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
Publication Release Date: Feb 2000
- 6 - Revision 0.50
ISA Interface Signals , continued
SYMBOL
PIN
MEMCS16#
12
I/O
INt
FUNCTION
Memory Chip Select 16.
MEMCS16# asserted indicates that the
memory slave supports 16-bit accesses.
I/O Channel Check.
IOCHK# can be driven by any resource on
the ISA bus during on detection of an error.
Zero Wait States.
An ISA slave asserts ZEROWS# after its
address and command signals have been decoded to indicate that
the current cycle can be executed as an ISA zero wait state cycle.
ZEROWS# has no effect during 16-bit I/O cycles.
Unlatched Address.
The LA[23:17] address lines are
bi-directional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs
when the W83628F owns the ISA Bus.
IOCHCK#
76
INt
OWS#
81
INt
LA[23:17]
103-1
04
106-1
09
111
82
OUT24
SMEMW#
OUT24
Standard Memory Write.
SMEMW# asserted indicates the
current ISA bus cycle is a memory write cycle to an address below
1 Mbyte.
Standard Memory Read.
SMEMR# asserted indicates the
current ISA bus cycle is a memory read cycle to an address below
1 Mbyte.
Refresh.
REFRESH# asserted indicates that a refresh cycle is in
progress, or that an ISA master is requesting W83626F to
generate a refresh cycle. Upon PCIRST#, this signal is tri-stated.
Bus Address Latch Enable.
BALE is an active high signal
asserted by the W83626F to indicate that the address (SA[19:0],
LA[23:17]) and SBHE# signal lines are valid.
The LA[23:17] address lines are latched on the trailing edge of
BALE. BALE remains asserted throughout DMA and ISA master
cycles. BALE is driven low upon PCIRST#.
System Byte High Enable.
SBHE# asserted indicates that a byte
is being transferred on the upper byte (SD[15:8]) of the data bus.
SBHE# is at an unknown state upon PCIRST#.
Memory Read.
MEMR# asserted indicates the current ISA bus
cycle is a memory read.
Memory Write.
MEMW# asserted indicates the current ISA bus
cycle is a memory write.
MASTER#.
This signal is used with a DREQ line by an ISA master
to gain control of the ISA Bus.
RTC Function Enable.The pin applies a pull-down resistor (4.7K
ohm) to enable RTC functions ( RTCCS#,and IRQ8)
Parallel Interrupt Requested Input 3.
SMEMR#
83
OUT24
REFRESH#
91
OUT24
BALE
101
OUT24
SBHE#
102
OUT24
MEMR#
112
OUT24
MEMW#
113
OUT24
MASTER#
RTCEN#
123
INt
IRQ3
98
INt
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相關代理商/技術參數(shù) |
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| W83626F_05 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC TO ISA BRIDGE SET |
| W83626G | 功能描述:IC LPC TO ISA BRIDGE 128-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:* 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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| W83627DHG-P | 制造商:Nuvoton Technology Corp 功能描述:I/O Controller LPC Controller 128-Pin QFP 制造商:Nuvoton Technology Corp 功能描述:IC I/O CONTROLLER 128-QFN |
| W83627DHG-P(FA5B07 D) | 制造商:Nuvoton Technology Corp 功能描述:IC I/O CONTROLLER 128-QFP |
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