
W83977F/ W83977AF
PRELIMINARY
Publication Release Date: March 1998
-7 -
Revision 0.58
1.1 Host Interface, continued
SYMBOL
PIN
I/O
FUNCTION
DACK0
GP16
(WDTO)
P15
RTSC
119
IN
ts
I/O
12t
I/O
12t
OUT
12t
CR2C bit5, 4= 00 (default): DMA Channel 0 Acknowledge
signal.
CR2C bit5, 4= 01: General purpose I/O port 1 bit 6. It can be
configured as a watchdog timer output.
CR2C bit5, 4= 10: Keyboard P15 I/O port.
CR2C bit5, 4= 11: RTS output of UART C.
[W83977AF only]
DRQ0
GP17
(PLEDO)
P14
DTRC
121
OUT
12t
I/O
12t
I/O
12t
OUT
12t
CR2C bit7, 6= 00 (default): DMA Channel 0 request signal.
CR2C bit7, 6= 01: General purpose I/O port 1, bit 7. It can be
configured as power LED output.
CR2C bit7, 6= 10: Keyboard P14 I/O port.
CR2C bit7, 6= 11: DTR output of UART C.
[W83977AF only]
DACK1
DRQ1
122
IN
ts
DMA Channel 1 Acknowledge signal
123
OUT
12t
IN
ts
DMA Channel 1 request signal
DACK2
DRQ2
124
DMA Channel 2 Acknowledge signal
125
OUT
12t
IN
ts
DMA Channel 2 request signal
DACK3
DRQ3
126
DMA Channel 3 Acknowledge signal
127
OUT
12t
IN
ts
DMA Channel 3 request signal
TC
128
Terminal Count. When active, this pin indicates termination of a
DMA transfer.
IRQ1
99
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
Interrupt request 1
IRQ3
98
Interrupt request 3
IRQ4
97
Interrupt request 4
IRQ5
96
Interrupt request 5
IRQ6
95
Interrupt request 6
IRQ7
94
Interrupt request 7
IRQ8/ nIRQ8
93
Interrupt request 8; default is nIRQ8 for RTC
IRQ9
92
Interrupt request 9
IRQ10
100
Interrupt request 10
IRQ11
101
Interrupt request 11
IRQ12
102
Interrupt request 12