
W83977F/ W83977AF
PRELIMINARY
Publication Release Date: March 1998
- 64 -
Revision 0.58
4.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced IR
Reset Value
0
0
0
0
TXFD5
0
TXFD4
0
TXFD3
0
TXFD2
0
TXFD1
0
TXFD1
0
Bit 7~6:
Bit 5~0:
Reserved,
Read 0.
Reading these bits returns the current transmitter FIFO depth, that is, the number of
bytes left in the transmitter FIFO.
4.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only)
Mode
Bit 7
0
0
Bit 6
0
0
Bit 5
RXFD5
0
Bit 4
RXFD4
0
Bit 3
RXFD3
0
Bit 2
RXFD2
0
Bit 1
RXFD1
0
Bit 0
RXFD1
0
Advanced IR
Reset Value
Bit 7~6:
Bit 5~0:
Reserved,
Read 0.
Reading these bits returns the current receiver FIFO depth, that is, the number of bytes
left in the receiver FIFO.
4.5 Set3 - Version ID
and
Mapped Control Registers
Address Offset
0
1
2
3
4
5
6
7
Register Name
AUID
MP_UCR
MP_UFR
SSR
Reversed
Reserved
Reserved
Reserved
Register Description
Advanced IR ID
Mapped IR Control Register
Mapped IR FIFO Control Register
Sets Select Register
-
-
-
-
4.5.1 Reg0 - Advanced IR ID (AUID)
This register is read only. It stores advanced IR version ID. Reading it returns 1XH.
Reg.
Bit 7
Bit 6
Bit 5
SSR
SSR7
SSR6
SSR5
Default Value
0
0
0
Bit 4
SSR4
1
Bit 3
SSR3
X
Bit 2
SSR2
X
Bit 1
SRR1
X
Bit 0
SRR0
X
4.5.2 Reg1 - Mapped IR Control Register (MP_UCR)
This register is read only. Reading this register returns IR Control Register value of Set 0.
Reg.
Bit 7
Bit 6
Bit 5
SSR
SSR7
SSR6
SSR5
Default Value
0
0
0
Bit 4
SSR4
0
Bit 3
SSR3
0
Bit 2
SSR2
0
Bit 1
SRR1
0
Bit 0
SRR0
0