
W83977F/ W83977AF
PRELIMINARY
Publication Release Date: March 1998
- 57 -
Revision 0.58
Advanced IR:
Bit 7, 6:
RXFTL1, 0 - Receiver FIFO Threshold Level
Its definition is the same as Legacy IR. RXTH_I becomes 1 when the Receiver FIFO
Threshold Level is equal or larger than the defined value shown as follow.
RXFTL1, 0
(Bit 7, 6)
00
01
10
11
RX FIFO Threshold Level
(
FIFO Size:
16-byte
)
1
4
8
14
RX FIFO Threshold Level
(
FIFO Size:
32-byte
)
1
4
16
26
Note that the FIFO Size is selectable in SET2.Reg4.
TXFTL1, 0 - Transmitter FIFO Threshold Level
TXTH_I (Transmitter Threshold Level Interrupt) is set to 1 when the Transmitter
Threshold Level is less than the programmed value shown as follows.
Bit 5, 4:
TXFTL1, 0
(Bit 5, 4)
00
01
10
11
TX FIFO Threshold Level
(
FIFO Size:
16-byte
)
1
3
9
13
TX FIFO Threshold Level
(
FIFO Size:
32-byte
)
1
7
17
25
Bit 3 ~0
Same as in Legacy IR Mode
4.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR):
These two registers share the same address. In all Register Sets,
Set Select Register (SSR)
can be
programmed to select a desired Set but IR Control Register can only be programmed in Set 0 and Set
1. In other words, writing to Reg3 in Sets other than Set 0 and Set 1 will not affect IR Control
Register. The mapping of entry Set and programming value is shown as follows.
SSR Bits
3
Selected
Set
7
6
5
4
2
1
0
Hex
Value
D
D
0xE0
0xE4
0xE8
0xEC
0xF0
0xF4
0
1
1
1
1
1
1
1
Set 0
Set1
Set 2
Set 3
Set 4
Set 5
Set 6
Set 7
Any combination except those used in SET 2~7
1
0
0
1
0
0
1
0
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0