
W83977F/ W83977AF
PRELIMINARY
Publication Release Date: March 1998
- 70 -
Revision 0.58
4.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)
This register controls ASK-IR, MIR, FIR operations.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IR_CFG2 SHMD_N SHDM_N FIR_CRC MIR_CRC
0
0
-
0
INV_CRC DIS_CRC
0
-
0
Reset Value
1
0
0
Bit 7:
SHMD_N - ASK-IR Modulation Disable
SHMD_N
0
1
SHDM_N - ASK-IR Demodulation Disable
SHDM_N
0
1
FIR_CRC - FIR (4M bps) CRC Type
FIR_CRC
0
1
Note that the 16/32-bit CRC are defined in IrDA 1.1 physical layer.
MIR_CRC - MIR (1.152M/0.576M bps) CRC Type
MIR_CRC
0
1
INV_CRC - Inverting CRC
When set to 1, the CRC is inversely output in physical layer.
DIS_CRC - Disable CRC
When set to 1, the transmitter does not transmit CRC in physical layer.
Reserved
, write 1.
Modulation Mode
IRTX modulate 500K Hz Square Wave
Re-rout IRTX
Bit 6:
Demodulation Mode
Demodulation 500K Hz
Re-rout IRRX
Bit 5:
CRC Type
16-bit CRC
32-bit CRC
Bit 4:
CRC Type
16-bit CRC
32-bit CRC
Bit 2:
Bit 1:
Bit 0:
4.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width
Reg.
MIR_PW
Reset Value
This 5-bit register sets MIR output pulse width.
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
M_PW4
0
Bit 3
M_PW3
1
Bit 2
M_PW2
0
Bit 1
M_PW1
1
Bit 0
M_PW0
0
M_PW4~0
00000
00001
00010
...
k
10
...
11111
MIR Pulse Width
(1.152M bps)
0
ns
20.83
ns
41.66
(==20.83*2) ns
...
20.83*
k
10
ns
...
645
ns
MIR Output Width
(0.576M bps)
0
ns
41.66
ns
83.32
(==41.66*2) ns
...
41.66*
k
10
ns
...
1290
ns