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參數資料
| 型號： | W982516BH |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 4M X 4 BANKS X 16 BIT SDRAM |
| 中文描述： | 4米× 4銀行× 16位SDRAM |
| 文件頁數： | 11/43頁 |
| 文件大小： | 1570K |
| 代理商： | W982516BH |
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W982516BH
Publication Release Date: December 13, 2001
- 11 -
Revision A2
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1) , (2))
COMMAND
DEVICE
STATE
CKEN-1
CKEN
DQM
BS0, 1
A10
A0
-
A9
A11, A12
CS
RAS
CAS
WE
Bank Active
Idle
H
x
x
v
v
v
L
L
H
H
Bank Precharge
Any
H
x
x
v
L
x
L
L
H
L
Precharge All
Any
H
x
x
x
H
x
L
L
H
L
Write
Active (3)
H
x
x
v
L
v
L
H
L
L
Write with Auto Precharge
Active (3)
H
x
x
v
H
v
L
H
L
L
Read
Active (3)
H
x
x
v
L
v
L
H
L
H
Read with Auto Precharge
Active (3)
H
x
x
v
H
v
L
H
L
H
Mode Register Set
Idle
H
x
x
v
v
v
L
L
L
L
No-operation
Any
H
x
x
x
x
x
L
H
H
H
Burst Stop
Active (4)
H
x
x
x
x
x
L
H
H
L
Device Deselect
Any
H
x
x
x
x
x
H
x
x
x
Auto Refresh
Idle
H
H
x
x
x
x
L
L
L
H
Self Refresh Entry
Idle
H
L
x
x
x
x
L
L
L
H
Self Refresh Exit
Idle
(S.R.)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Clock Suspend Mode
Entry
Active
H
L
x
x
x
x
x
x
x
x
Power-down Mode Entry
Idle
Active (5)
H
H
L
L
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Clock Suspend Mode Exit
Active
L
H
x
x
x
x
x
x
x
x
Power-down Mode Exit
Any
(Power-
down)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Data Write/Output Enable
Active
H
x
L
x
x
x
x
x
x
x
Data Write/Output Disable
Active
H
x
H
x
x
x
x
x
x
x
Notes:
(1) v = valid x = Don't care L = Low Level H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power-down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
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