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參數資料
| 型號： | W982516BH |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 4M X 4 BANKS X 16 BIT SDRAM |
| 中文描述： | 4米× 4銀行× 16位SDRAM |
| 文件頁數： | 15/43頁 |
| 文件大小： | 1570K |
| 代理商： | W982516BH |
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W982516BH
Publication Release Date: December 13, 2001
- 15 -
Revision A2
Auto Precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto precharge function is
entered. During auto precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto precharge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during
a read or write cycle with auto precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (t
RP
) has been satisfied. Issue of Auto precharge command is
illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto precharge function is initiated. The SDRAM automatically enters the precharge operation
one clock delay from the last burst write cycle. This delay is referred to as Write t
WR
. The bank
undergoing auto precharge can not be reactivated until t
WR
and t
RP
are satisfied. This is referred to as
t
DAL
, Data-in to Active delay (t
DAL
= t
WR
+ t
RP
). When using the Auto precharge Command, the interval
between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy t
RAS
(min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of
the clock. The Precharge Command can be used to precharge each bank separately or all banks
simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(t
RP
).
Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at
the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once
the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the
SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled.
The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self
Refresh operation after CKE is returned high. A minimum delay time is required when the device exits
Self Refresh Operation and before the next command can be issued. This delay is equal to the t
AC
cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 8,192 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
Power-down Mode
The Power-down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power-down mode does not perform any refresh operations,
therefore the device can not remain in Power-down mode longer than the Refresh period (t
REF
) of the
device.
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相關代理商/技術參數 |
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| W982516BH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M X 4 BANKS X 16 BIT SDRAM |
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| W982516BH75I | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M X 4 BANKS X 16 BIT SDRAM |
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| W9825G2JB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M ? 4 BANKS ? 32BITS SDRAM |
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