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參數資料
| 型號： | W986432AH |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 512K x 4 BANKS x 32 BITS SDRAM |
| 中文描述： | 為512k × 4銀行× 32位內存 |
| 文件頁數： | 3/11頁 |
| 文件大小： | 79K |
| 代理商： | W986432AH |
W986432DH
Publication Release Date: May 2000
- 3 -
Revision A0
DQM0
DQM3
Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency.
CLK
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
V
CC
Power (+3.3V)
Power for input buffers and logic circuit inside DRAM.
V
SS
Ground
Ground for input buffers and logic circuit inside DRAM.
V
CCQ
Power (+3.3V) for
I/O buffer
Separated power from V
CC
, to improve DQ noise immunity.
V
SSQ
Ground for I/O
buffer
Separated ground from V
SS
, to improve DQ noise immunity.
NC
No Connection
No connection
相關PDF資料 |
PDF描述 |
|---|---|
| W986432AH-55 | x32 SDRAM |
| W986432AH-6 | x32 SDRAM |
| W986432AH-7 | x32 SDRAM |
| W986432AH-8 | x32 SDRAM |
| W9864AADA | 64MB (8M x 64) PC100 SDRAM MODULE(符合PC100標準的64MB (8M x 64) 同步動態RAM模塊) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W986432AH-55 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x32 SDRAM |
| W986432AH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x32 SDRAM |
| W986432AH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x32 SDRAM |
| W986432AH-8 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x32 SDRAM |
| W986432DH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K ⅴ 4 BANKS ⅴ 32 BITS SDRAM |
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