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參數(shù)資料
| 型號： | W986432AH |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 512K x 4 BANKS x 32 BITS SDRAM |
| 中文描述： | 為512k × 4銀行× 32位內(nèi)存 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 79K |
| 代理商： | W986432AH |
W986432DH
- 8 -
AC CHARACTERISTICS
(V
CC
= 3.3V
±
0.3V, V
SS
= 0V, Ta = 0 to 70
°
C) (Notes: 5, 6.)
PARAMETER
Symbol
tRC
tRAS
-7
-8
UNIT NOTE
ns
Cycle
MIN
65
45
20
1
MAX
100000
MIN
68
48
20
1
MAX
100000
MIN
MAX
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time tRCD
Read/Write(a) to Read/Write(b)Command
Period
Precharge to Active(b) Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
CLK Cycle Time
tCCD
tRP
tRRD
tWR
tCK
tCH
tCL
tAC
tOH
tHZ
tLZ
tSB
tT
tDS
tDH
tAS
tAH
tCKS
tCKH
tCMS
tCMH
tREF
tRSC
20
14
7.5
7
7.5
7
2
2
3
3
0
0
0.5
0.5
1
0.5
1
0.5
1
0.5
1
14
20
20
10
8
10
8
3
3
3
3
0
0
0.5
2
1
2
1
2
1
2
1
16
ns
ms
ns
CL* = 2
CL* = 3
CL* = 2
CL* = 3
1000
1000
5.5
5
7
7
10
64
1000
1000
6
6
8
8
10
64
CLK High Level
CLK Low Level
Access Time from CLK
Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in-Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode Register Set Cycle Time
CL* = 2
CL* = 3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W986432AH-55 | x32 SDRAM |
| W986432AH-6 | x32 SDRAM |
| W986432AH-7 | x32 SDRAM |
| W986432AH-8 | x32 SDRAM |
| W9864AADA | 64MB (8M x 64) PC100 SDRAM MODULE(符合PC100標(biāo)準(zhǔn)的64MB (8M x 64) 同步動態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W986432AH-55 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x32 SDRAM |
| W986432AH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x32 SDRAM |
| W986432AH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x32 SDRAM |
| W986432AH-8 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x32 SDRAM |
| W986432DH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K ⅴ 4 BANKS ⅴ 32 BITS SDRAM |
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