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參數資料
| 型號： | W9864AADA |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64MB (8M x 64) PC100 SDRAM MODULE(符合PC100標準的64MB (8M x 64) 同步動態RAM模塊) |
| 中文描述： | 64MB的（8米× 64）PC100的SDRAM內存模組（符合PC100的標準的64MB的（8米× 64）同步動態內存模塊） |
| 文件頁數： | 3/12頁 |
| 文件大小： | 173K |
| 代理商： | W9864AADA |
W9864AADA
64MB (8M x 64) PC100 SDRAM MODUL
E
Pin Description
Revision 0.9
3 OF
12
Publication Release Date:98/05/18
Pin
CLKn
Name
Function Description
Clock Inputs
System clock used to sample inputs on the rising edge of clock.
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self-Refresh mode is entered.
Multiplexed pins for row and column address.
Row address: A0~A11. Column address: A0~A7.
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Command input. When sampled at the rising edge of the clock, RAS#,
CAS# and WE# define the operation to be executed.
Referred to RAS#
Referred to RAS#
The output buffer is placed at Hi-Z when DQM is sampled high in read
cycle. In write cycle, sampling DQM high will block the write data.
Multiplexed pins for data output and input
Power for input buffers and logic circuit inside SDRAM.
Ground for input buffers and logic circuit inside SDRAM.
Clock for serial presence detection
Data line for serial presence detection
System assigned address (SA0~SA2) to identify different memory module
in a system board.
No connection
CSn#
Chip select
CKEn
Clock Enable
A0~A11
Address
BA0~BA1
Bank Select Address
RAS#
Row Address Strobe
CAS#
WE#
Column Address Strobe
Write Enable
DQM0~7
Input/Output Mask
DQ0~63
V
DD
V
SS
SCL
SDA
Data Input/Output
Power (+3.3 V)
Ground
Serial Clock
Serial Data I/O
SAn
SPD Address Line
NC
No Connection
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