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參數資料
| 型號： | W9864AADA |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64MB (8M x 64) PC100 SDRAM MODULE(符合PC100標準的64MB (8M x 64) 同步動態RAM模塊) |
| 中文描述： | 64MB的（8米× 64）PC100的SDRAM內存模組（符合PC100的標準的64MB的（8米× 64）同步動態內存模塊） |
| 文件頁數： | 7/12頁 |
| 文件大小： | 173K |
| 代理商： | W9864AADA |
W9864AADA
64MB (8M x 64) PC100 SDRAM MODUL
E
Revision 0.9
7 OF
12
Publication Release Date:98/05/18
AC CHARACTERISTICS AND OPERATING CONDITION
( Vcc=3.3V
±
0.3V, Ta=0
°
to 70
°
C )
-8H
-8N
- 10
SYMBOL
PARAMETER
MIN
68
48
20
MAX
MIN
72
48
20
MAX
MIN
90
60
30
MAX
UNIT
t
RC
t
RAS
t
RCD
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b)Command
Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
100000
100000
100000
ns
t
CCD
1
1
1
cycle
t
RP
t
RRD
20
20
10
8
10
8
3
3
20
20
12
10
12
10
3
3
30
20
15
10
15
10
3
3
CL*=2
CL*=3
CL*=2
CL*=3
t
WR
CLK Cycle Time
1000
1000
1000
1000
t
CK
t
CH
t
CL
CLK High Level
CLK Low Level
Access Time from CLK
CL*=2
CL*=3
6
6
7
6
9
8
t
AC
t
OH
t
HZ
**
t
LZ
t
SB
t
T
t
DS
t
DH
t
AS
t
AH
t
CKS
t
CKH
t
CMS
t
CMH
t
REF
t
RSC
Note:
*CL=CAS Latency
** t
HZ
defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
Refer to the individual component
Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in-Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time
3
3
0
0
3
3
0
0
3
3
0
0
8
8
10
8
8
10
10
10
0.5
2
1
2
1
2
1
2
1
10
0.5
2
1
2
1
2
1
2
1
0.5
3
1
3
1
3
1
3
1
ns
64
64
64
ms
ns
16
16
20
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