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參數資料
| 型號： | WFP6540B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 顯示驅動器 |
| 英文描述： | 258-Channel, 6-Bit Signal Driver for XGA COG（chip-on-glass）TFT-LCDs Applications(用XGA COG TFT型液晶顯示器的258通道的，6位信號驅動器) |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC305 |
| 封裝： | DIE-305 |
| 文件頁數： | 14/25頁 |
| 文件大小： | 648K |
| 代理商： | WFP6540B |
14
1999 Winbond Electronics Corporation
October 5, 1999
Rev. 0.01
WFP6540B
258-Channel COG Signal Driver for XGA TFT-LCDs
Name
Number
Type
Description
(Cont.)
V
S1
-V
S258
42-300
O
VOLTAGE OUTPUTS
: These outputs drive all 258 pixel
inputs of the LCD simultaneously after the high-to-low tran-
sition of LP. Outputs are high impedance while LP is high.
D
05
-D
00
D
15
-D
10
D
25
-D
20
35-40
8,13,14,27-29
2-7
I
DATA
: The Data inputs consist of 6-bit words for each of
three channels. At the falling edge of DCLK, three 6-bit
words for three adjacent channels are loaded in parallel.
Each data bit is represented as Dij where:
i = 2-0 indicates the channel
j = 5-0 indicates the significance of the bit in each word.
D
i5
indicates the MSB and D
i0
indicates the LSB of the input
word.
LP
34
I
Latch Pulse
: When LP is asserted, the data is transferred
from the Input Register into the Storage Register, and the
selected analog voltages drive the LCD. The EIOx# output
is reset to the ‘high’ level.
DCLK
15
I
DATA CLOCK
: Data is loaded into the input registers on the
high-to-low transition of DCLK for 2xCLK= low and on both
rising and falling edges of DCLK for 2xCLK = high.
CLAMP#
30
I
CLAMP
: The CLAMP# input controls the active pulldown
devices which are present on the DCLK and D
00
-D
25
inputs.
When the CLAMP# signal drives low, these clamp devices
connect DCLK and D
00
-D
25
to the WFP6540B’s GND
through a low impedance.
The CLAMP# pin should be
connected to V
DDD
in applications where level shifting
is not used (i.e. when V
COM
modulation is employed).
V
DDD
16
I
DIGITAL SUPPLY VOLTAGE
: Either 3.3 V or 5.0 V should
be provided on this pin to supply digital power to the device.
V
DDA
17
I
ANALOG SUPPLY VOLTAGE
: Up to 5.0 V should be pro-
vided on this pin to supply analog power to the device.
V
8
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
11,31
18
23
20
21
22
19
24
10,32
I
REFERENCE ANALOG VOLTAGE INPUTS:
These
nine inputs are used to supply the adjustable-reference volt-
age inputs to the resistive-string DAC to provide the trans-
missivity-voltage response required for each type of LCD.
Note: both V
8
pads must be connected to each other
and to the same potential; also, both V
0
pads must be .
connected to each other and to the same potential
A
GND
25
I
ANALOG
GROUND
D
GND
26
I
DIGITAL GROUND
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