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參數(shù)資料
| 型號： | AD7854L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit Sampling ADC(單電源,200kSPS 12位采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 12位采樣ADC（單電源，速度高達(dá)200ksps的12位采樣的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 22/28頁 |
| 文件大小： | 268K |
| 代理商： | AD7854L |
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AD7854/AD7854L
–22–
REV. 0
System Gain and Offset Interaction
T he architecture of the AD7854/AD7854L leads to an interac-
tion between the system offset and gain errors when a system
calibration is performed. T herefore it is recommended to per-
form the cycle of a system offset calibration followed by a sys-
tem gain calibration twice. When a system offset calibration is
performed, the system offset error is reduced to zero. If this is
followed by a system gain calibration, then the system gain error
is now zero, but the system offset error is no longer zero. A sec-
ond sequence of system offset error calibration followed by a
system gain calibration is necessary to reduce system offset error
to below the 12-bit level. T he advantage of doing separate sys-
tem offset and system gain calibrations is that the user has more
control over when the analog inputs need to be at the required
levels, and the
CONVST
signal does not have to be used.
Alternatively, a system (gain + offset) calibration can be per-
formed. At the end of one system (gain + offset) calibration, the
system offset error is zero, while the system gain error is reduced
from its initial value. T hree system (gain + offset) calibrations
are required to reduce the system gain error to below the 12-bit
error level. T here is never any need to perform more than three
system (gain + offset) calibrations.
In bipolar mode the midscale error is adjusted for an offset cali-
bration and the positive full-scale error is adjusted for the gain
calibration; in unipolar mode the zero-scale error is adjusted for
an offset calibration and the positive full-scale error is adjusted
for a gain calibration.
System Calibration T iming
T he timing diagram in Figure 33 is for a software full system
calibration. It may be easier in some applications to perform
separate gain and offset calibrations so that the
CONVST
bit in
the control register does not have to be programmed in the
middle of the system calibration sequence. Once the write to the
control register setting the bits for a full system calibration is
completed, calibration of the internal DAC is initiated and the
BUSY line goes high. T he full-scale system voltage should be
applied to the analog input pins, AIN(+) and AIN(–) at the start
of calibration. T he BUSY line goes low once the DAC and
system gain calibration are complete. Next the system offset
voltage should be applied across the AIN(+) and AIN(–) pins
for a minimum setup time (t
SET UP
) of 100 ns before the rising
edge of
CS
. T his second write to the control register sets the
CONVST
bit to 1 and at the end of this write operation the
BUSY signal is triggered high (note that a
CONVST
pulse can
be applied instead of this second write to the control register).
T he BUSY signal is low after a time t
CAL2
when the system offset
calibration section is complete. T he full system calibration is now
complete.
T he timing for a system (gain + offset) calibration is very similar
to that of Figure 33, the only difference being that the time
t
CAL 1
is replaced by a shorter time of the order of t
CAL 2
as the
internal DAC is not calibrated. T he BUSY signal signifies when
the gain calibration is finished and when the part is ready for the
offset calibration.
CONVST BIT SET
TO 1 IN CONTROL
REGISTER
t
23
DATA LATCHED INTO
CONTROL REGISTER
Hi-Z
Hi-Z
Hi-Z
t
CAL1
t
23
t
SETUP
V
OFFSET
V
SYSTEM FULL SCALE
DATA
CS
WR
DATA
BUSY
AIN
DATA
t
CAL2
Figure 33. Timing Diagram for Full System Calibration
T he timing diagram for a system offset or system gain calibra-
tion is shown in Figure 34. Here again a write to the control reg-
ister initiates the calibration sequence. At the end of the control
register write operation the BUSY line goes high and it stays
high until the calibration sequence is finished. T he analog input
should be set at the correct level for a minimum setup time
(t
SET UP
) of 100 ns before the
CS
rising edge and stay at the cor-
rect level until the BUSY signal goes low.
t
23
Hi-Z
Hi-Z
DATA LATCHED INTO
CONTROL REGISTER
t
SETUP
t
CAL2
DATA
VALID
V
SYSTEM FULL SCALE
OR V
OFFSET
CS
WR
DATA
BUSY
AIN
Figure 34. Timing Diagram for System Gain or System
Offset Calibration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7854 | 12-Bit Sampling ADC(單電源,200kSPS 12位采樣A/D轉(zhuǎn)換器) |
| AD7858LARS | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| AD7858BN | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| AD7858BR | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| AD7858AN | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7854LAQ | 制造商:Rochester Electronics LLC 功能描述:12 BIT SINGLE CHANNEL PARALLEL ADC I.C. - Bulk |
| AD7854LAR | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:12-BIT SINGLE CHANNEL PARALLEL ADC I.C. - Bulk |
| AD7854LAR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 12-BIT PARALLEL 28SOIC W - Tape and Reel |
| AD7854LARS | 功能描述:IC ADC 12BIT PARALLEL LP 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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