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參數資料
| 型號： | AD7854L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit Sampling ADC(單電源,200kSPS 12位采樣A/D轉換器) |
| 中文描述： | 12位采樣ADC（單電源，速度高達200ksps的12位采樣的A / D轉換器） |
| 文件頁數： | 9/28頁 |
| 文件大小： | 268K |
| 代理商： | AD7854L |
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AD7854/AD7854L
REV. 0
–9–
CONT ROL RE GIST E R
T he arrangement of the control register is shown below. T he control register is a write only register and contains 14 bits of data. T he
control register is selected by putting two 1s in ADDR1 and ADDR0. T he function of the bits in the control register is described be-
low. T he power-up status of all bits is 0.
MSB
ZERO
ZERO
ZERO
ZERO
PMGT 1
PMGT 0
RDSLT 1
RDSLT 0
AMODE
CONVST
CALMD
CALSLT 1
CALSLT 0
ST CAL
LSB
Control Register Bit Function Description
Bit
Mnemonic
Comment
13
12
11
10
9
8
7
6
5
ZERO
ZERO
ZERO
ZERO
PMGT 1
PMGT 0
RDSLT 1
RDSLT 0
AMODE
T hese four bits must be set to 0 when writing to the control register.
Power Management Bits. T hese two bits are used for putting the part into various power-down modes
(See
Power-Down
section for more details).
T heses two bits determine which register is addressed for the read operations. See T able II.
Analog Mode Bit. T his pin allows two different analog input ranges to be selected. A logic 0 in this bit
position selects range 0 to V
REF
(i.e., AIN(+) – AIN(–) = 0 to V
REF
). In this range AIN(+) cannot go
below AIN(–) and AIN(–) cannot go below AGND and data coding is straight binary. A logic 1 in this
bit position selects range –V
REF
/2 to +V
REF
/2 (i.e., AIN(+) – AIN(–) = –V
REF
/2 to +V
REF
/2). AIN(+)
cannot go below AGND, so for this range, AIN(–) needs to be biased to at least +V
REF
/2 to allow
AIN(+) to go as low as AIN(–) –V
REF
/2 V. Data coding is twos complement for this range.
Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-
cally reset to 0 at the end of conversion. T his bit may also used in conjunction with system calibration
(see Calibration section).
Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see T able III).
Calibration Selection Bits and Start Calibration Bit. T hese bits have two functions.
With the ST CAL bit set to 1, the CALSLT 1 and CALSLT 0 bits determine the type of calibration per-
formed by the part (see T able III). T he ST CAL bit is automatically reset to 0 at the end of calibration.
With the ST CAL bit set to 0, the CALSLT 1 and CALSLT 0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on the calibration registers for more details).
4
CONVST
3
2
1
0
CALMD
CALSLT 1
CALSLT 0
ST CAL
T able III. Calibration Selection
CALMD
CALSLT 1
CALSLT 0
Calibration T ype
0
0
0
A
full internal calibration
is initiated. First the internal DAC is calibrated, then the
internal gain error and finally the internal offset error are removed. T his is the default setting.
First the
internal gain error
is removed, then the
internal offset error
is removed.
T he
internal offset error
only is calibrated out.
T he
internal gain error
only is calibrated out.
A
full system calibration
is initiated. First the internal DAC is calibrated, followed by the
system gain error calibration, and finally the system offset error calibration.
First the
system gain error
is calibrated out followed by the
system offset error
.
T he
system offset error
only is removed.
T he
system gain error
only is removed.
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
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相關代理商/技術參數 |
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|---|---|
| AD7854LAQ | 制造商:Rochester Electronics LLC 功能描述:12 BIT SINGLE CHANNEL PARALLEL ADC I.C. - Bulk |
| AD7854LAR | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:12-BIT SINGLE CHANNEL PARALLEL ADC I.C. - Bulk |
| AD7854LAR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 12-BIT PARALLEL 28SOIC W - Tape and Reel |
| AD7854LARS | 功能描述:IC ADC 12BIT PARALLEL LP 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
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