
The Western Design Center, Inc.
W65C02S Datasheet
The Western Design Center, Inc., W65C02S Datasheet 25
6.2
AC Characteristics TA = -40
°
C to +85
°
C (PLCC, QFP) TA= 0
°
C to 70
°
C (DIP)
Table 6-3 AC Characteristics
5.0 +/-5%
14MHz
Min
3.3 +/-10%
8MHz
Min
3.0 +/-5%
8MHz
Min
2.5 +/-5%
4MHz
Min
1.8 +/-5%
2MHz
Min
Symbol
Parameter
Max
Max
Max
Max
Max
Units
VDD
Supply Voltage
4.75
5.25
3.0
3.6
2.85
3.15
2.375
2.675
1.71
1.89
V
tACC
Access Time
30
-
70
-
70
-
145
-
290
-
nS
tAH
Address Hold Time
10
-
10
-
10
-
10
-
10
-
nS
tADS
Address Setup Time
-
30
-
40
-
40
-
75
-
150
nS
tBVD
BE to Valid Data (1)
-
25
-
30
-
30
-
30
-
30
nS
CEXT
Capacitive Load (2)
-
35
-
35
-
35
-
35
-
35
pF
tPWH
Clock Pulse Width High
35
-
62
-
62
-
125
-
250
-
nS
tPWL
Clock Pulse Width Low
35
-
63
-
63
-
125
-
250
-
nS
tCYC
Cycle Time (3)
70
-
125
-
125
-
250
-
500
-
nS
tF,tR
Fall Time, Rise Time
-
5
-
5
-
5
-
5
-
5
nS
tPCH
Processor Control Hold Time
10
-
10
-
10
-
10
-
10
-
nS
tPCS
Processor Control Setup Time
10
-
15
-
15
-
30
-
60
-
nS
tDHR
Read Data Hold Time
10
-
10
-
10
-
10
-
10
-
nS
tDSR
Read Data Setup Time
10
-
15
-
15
-
30
-
60
-
nS
tMDS
Write Data Delay Time
-
25
-
40
-
40
-
70
-
140
nS
tDHW
Write Data Hold Time
10
-
10
-
10
-
10
-
10
-
nS
1. BE to High Impedance State is not testable but should be the same amount of time as BE to Valid Data
2.
ATE or loading on all outputs
3.
Since this is a static design, the maximum cycle time could be infinite.