
The Western Design Center, Inc.
W65C02S Datasheet
Table 6-4 Operation, Operation Codes and Status Register
Operation
# Immediate Data
~ NOT
^
AND
v
OR
a
v
Exclusive OR
1
2
3
4
5
6
7
ADC
A+M+C
→
A
6D
7D
79
69
AND
A
^
M
→
A
2D
3D
39
29
ASL
C
←
7 6 5 4 3 2 1 0
←
0
0E
1E
0A
BBR0
Branch on bit 0 reset
BBR1
Branch on bit 1 reset
BBR2
Branch on bit 2 reset
BBR3
Branch on bit 3 reset
BBR4
Branch on bit 4 reset
BBR5
Branch on bit 5 reset
BBR6
Branch on bit 6 reset
BBR7
Branch on bit 7 reset
BBS0
Branch on bit 0 set
BBS1
Branch on bit 1 set
BBS2
Branch on bit 2 set
BBS3
Branch on bit 3 set
BBS4
Branch on bit 4 set
BBS5
Branch on bit 5 set
BBS6
Branch on bit 6 set
BBS7
Branch on bit 7 set
BCC
Branch C = 0
BCS
Branch if C = 1
BEQ
Branch if Z = 1
BIT
A
^
M
2C
3C
89
BMI
Branch if N = 0
BNE
Branch if Z = 0
BPL
Branch if N = 0
BRA
Branch Always
The Western Design Center, Inc. W65C02S Datasheet 28
Processor Status Register (P)
*User Defined
(
a
a
(
A
#
i
r
s
z
(
z
z
(
(
7
N
N
N
N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
M
7
M
6
.
.
.
6
V
V
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
5
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
4
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3
D
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
2
I
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Z
.
.
.
1
Z
Z
Z
Z
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
C
C
.
C
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
M
8
9
10
11
65
12
61
13
14
15
16
75
72
71
25
21
35
32
31
06
16
0F
1F
2F
3F
4F
5F
6F
7F
8F
9F
AF
BF
CF
DF
EF
FF
90
B0
F0
24
34
30
.
.
.
D0
10
80