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參數資料
| 型號： | W6612 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Dual PCM Codec(雙通道PCM編解碼器) |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 15/21頁 |
| 文件大小： | 161K |
| 代理商： | W6612 |
W6612
Publication Release Date: October 1998
- 15 -
Revision A1
7.5. Digital Switching Characteristics
7.5.1 Long frame and short frame sync timing
(V
DD
= 5
±
5% V; GNDD = 0V; all digital circuits referenced to GNDD; Top = -40 to +85
°
C, C
L
= 150 pF )
PARAMETER
SYM.
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Master Clock Frequency
T
MAST
MCLK
----
2.048
1.536
---
----
MHz
MHz
KHz
Bit Clock Frequency
T
BCLK
BCLKT1, BCLKT2,
BCLKR1, BCLKR2
FST1, FST2,
FSR1, FSR2
MCLK,
BCLKT1, BCLKT2,
BCLKR1, BCLKR2
All digital input pins
128
4096
Frame Sync. Frequency
T
SYNC
---
8
- -
KHz
Clock Duty Cycle
D
C
---
50
---
%
Rise Time
T
IR
---
---
50
nS
Fall Time
T
IF
All digital input pins
---
---
50
nS
Hold Time for 2nd cycle of
BCLKT1/2(BCLKR1/2)
Transmit Sync. Timing
T
HLD
BCLKT1/2(BCLKR1/2) Low
to FST1/2(FSR1/2) Low
BCLKT1/2 to FST1/2
FST1/2 to BCLKT1/2
BCLKR1/2 to FSR1/2
FSR1/2 to BCLKR1/2
---
50
---
---
nS
T
XS
T
SX
T
RS
T
SR
T
STDR
20
80
20
80
20
---
---
---
---
---
---
---
---
---
---
nS
Receive Sync. Timing
nS
Setup Time for DR1(DR2) Valid
nS
Hold Time for DR1(DR2) Valid
T
HDDR
---
50
---
---
nS
Output Delay Time for 1st
DT1(DT2) Valid
Output Delay Time for 2nd
DT1(DT2) Valid
Output Delay Time for
DT1(DT2) High Impedance
T
DV1
BCLKT1/2 to DT1/2
10
120
nS
T
DV2
BCLKT1/2 to DT1/2
10
---
120
nS
T
DHI
BCLKT1/2 to DT1/2
10
---
120
nS
Note: these parameters are shown in Figure 7-1 and 7-2.
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