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參數資料
| 型號： | W6612 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Dual PCM Codec(雙通道PCM編解碼器) |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 8/21頁 |
| 文件大小： | 161K |
| 代理商： | W6612 |
W6612
- 8 -
6.1.3. Reference Voltage Control System
All analog signal reference voltages such as OP amplifier is 2.5 volt.
6.2.
This device has built in dual linear 14-bit PCM codec-filter using
Σ
technology. There are two paths
in the block, a transmit path and a receive path.
Codec-filter
6.2.1. Transmit Path in
Σ
Codec-filter
The two analog signal inputs are passed to three terminal operational amplifiers (TG1, TG2) driving a
typical 2 K
load externally to amplify the input analog signal. Then the
Σ
ADC converts the analog
signal into linear 14-bit data.
6.2.2. Receive Path in
Σ
Codec-filter
Dual 14-bit linear digital signal from the digital conversion circuit is first passed to the
Σ
DAC block.
It will convert the 14-bit samples to the analog signal. Then the analog signal will reduce the spectral
components of the switched capacitor filter by the analog smoothing filter. Finally, the analog output
signal is sent to the power amplifier, RO1 or RO2, which is capable of driving a 2K
load connected
to to the analog ground.
Note the device provides another power amplifier, PO1 or PO2, connected in a push-pull
configuration. The PO1 or PO2 driver can accommodate large gain ranges by adjusting two external
resistors for applications such as driving a telephone line or a handset receiver.
6.3. Data Conversion
This block is the digital data convsersion circuit. There are two paths in this block, a transmit path and
a receive path.
6.3.1. Transmit Path in the Data Conversion
A linear 14 bit sample input from the transmit path of the
Σ
Codec-filter block is sent in two
processing directions: A/Mu law compressor, and Linear conversion selected by MODE1 and MODE0
pin. The mode selection refers to Table 6-1. In the A/Mu law compressor, the 14 bit linear data will
converted into 8-bit Log-PCM. In the Linear conversion, the 14-bit data will be sent into serial data
port directly. The final result outputs the PCM signal through pin DT1 or DT2 under the control of the
FST1 or FST2 (8K frame sync pulse) and BCLKT1 or BCLKT2 pins. The data output rate for BCLKT1
or BCLKT2 is from 128K to 4096 KHz.
MODE SELECTION
A-Law Compressor/Expander
Mu-Law Compressor/Expander
14-bit Linear Input/Output
14-bit Linear Input/Output
MODE1 PIN
0
0
1
1
MODE0 PIN
0
1
0
1
Table 6-1 The Mode Selection for the Data Conversion
6.3.2. Receive Path in the Data Conversion
The device receives PCM data from the DR1 or DR2 pin via the serial data port (SDP) under the
control of the BCLKR1 or BCLKR2 and FSR1 or FSR2 pins. The clock of the receive frame sync FSR
is 8 KHz. The serial data rate in the BCLKR1 or BCLKR2 is from 128 KHz to 4096 KHz range.
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