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參數資料
| 型號： | W6612 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Dual PCM Codec(雙通道PCM編解碼器) |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 6/21頁 |
| 文件大小： | 161K |
| 代理商： | W6612 |
W6612
- 6 -
4.3. PCM Serial Interface, continued
PIN NAME
BCLKT2
PIN NO.
25
I/O
I
FUNCTION
This pin is the transmit bit clock. It shifts out the data on the DT1
pin on the rising edge. The frequency may vary from 128K to 4096
KHz.
This pin is tri-state PCM output data for transmission controlled by
FST1 and BCLKT1 pin.
No connection for reservation
This pin is an 8K Hz pulse to receive the first frame syncs. It
enables the DR1 PCM input by BCLKR1 pin.
This pin is the receive bit clock. It shifts data on the DR1 pin into
the chip on the falling edge. The frequency varies from 128K to
4096 KHz.
This pin is the PCM receive input data controlled by the FSR1 and
BCLKR1 pins.
It is power down for Codec 1. When the pin is logic zero, all clocks
for codec1 are off and all bias current for codec 1 turn off.
This pin is power down for Codec 2. When the pin is logic zero, all
clocks for codec 2 are off and all bias current for codec 2 turn off.
This pin and MODE1 pin can select the PCM output mode including
A-law, Mu-law, linear 14 bit PCM.
This pin and MODE0 pin can select the PCM output mode including
A-law, Mu-law, linear 14 bit PCM.
DT2
23
O
NC
FSR2
22
20
O
I
BCLKR2
21
I
DR2
19
I
PDI1
17
I
PDI2
18
I
MODE0
15
I
MODE1
16
I
4.4. Miscellaneous
PIN NAME
PIN NO.
I/O
FUNCTION
TST1
38
I
This pin is internal pull-high test input pin. It is reserved by test
mode.
TST2
37
I
This pin is internal pull-high test input pin. It is reserved by test
mode.
TST3
36
I
This pin is internal pull-high test input pin. It is reserved by test
mode.
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