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參數資料
| 型號： | W741C260 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT Microcontroller(多次可編程4位的微控制器) |
| 中文描述： | 4-BIT, MROM, 4.19 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 19/92頁 |
| 文件大小： | 488K |
| 代理商： | W741C260 |
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W741C260
Publication Release Date: March 1998
- 19 -
Revision A3
HCF.0 = 1 Hold mode was released by overflow from the Divider0.
HCF.1 = 1 Hold mode was released by underflow from the Timer 0.
HCF.2 = 1 Hold mode was released by a signal change on port RC
HCF.3 Reservsd
HCF.4 = 1 Hold mode was released by overflow from the Divider 1.
HCF.5 = 1 Hold mode was released by underflow from the Timer 1.
HCF.6 & HCF.7 are reserved.
Event Flag (EVF)
The event flag is organized as an 8-bit binary register (EVF0 to EVF7). It is set by hardware and reset
by CLR EVF,#I instruction or the occurrence of an interrupt. The bit descriptions are as follows:
R
R
R
EVF
0
1
2
3
4
5
R
R
6
7
Note: R means read only.
EVF.0 = 1 Overflow from Divider 0 occurred.
EVF.1 = 1 Underflow from Timer 0 occurred.
EVF.2 = 1 Signal change on port RC occurred.
EVF.3 Reserved
EVF.4 = 1 Overflow from Divider 1 occurred.
EVF.5 & EVF.6 are reserved.
EVF.7 = 1 Underflow from Timer 1 occurred.
Parameter Flag (PMF)
The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled
by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:
W
0
1
2
3
PMF
Note: W means write only.
Bit 0, Bit1, Bit2
Bit 3 = 0 The fundamental frequency of the watchdog timer is F
OSC
/1024.
= 1 The fundamental frequency of the watchdog timer is F
OSC
/16384.
Reserved
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