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參數(shù)資料
| 型號(hào)： | W79E227APG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | ROHS COMPLIANT, PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 106/200頁(yè) |
| 文件大小： | 3644K |
| 代理商： | W79E227APG |
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Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 106 -
Revision A2.0
14.2 PWM Control Registers
The overall functioning of the PWM module is controlled by the contents of the PWMCON1 register.
The operation of most of the control bits is straightforward. For example PWM0I is an invert bit for
each output which causes results in the output to have the opposite value compared to its non-
inverted output. The transfer of the data from the Counter and Compare registers to the control
registers is controlled by the PWMCON1.6 (load) while PWMCON1.7 (PWMRUN) allows the PWM to
be either in the run or idle state.
If the Brake pin is not used to control the brake function, the “Brake when PWM is not running”
function can be used to cause the outputs to have a given state when the PWM is halted. This
approach should be used only in time critical situations when there is not sufficient time to use the
approach outlined above, since going from the Brake state to run without causing an undefined state
on the outputs is not straightforward. A discussion on this topic is included in the section on
PWMCON2.
The Brake function, which is controlled by the contents of the PWMCON2 register, is somewhat
unique. In general, when Brake is asserted, the eight PWM outputs are forced to a user selected state,
namely the state selected by PWMCON3. As shown in the description of the operation of the
PWMCON2 register, if PWMCON2.4, BKEN, is a “1” brake is asserted under the control
PWMCON2.7, BKCH, and PWMCON2.5, BPEN. As shown, if both are a “0”, brake is asserted. If
PWMCON2.7 is a “1”, brake is asserted when the PWMRUN bit, PWMCON1.7, is a “0”. If
PWMCON2.6, BKPS, is a “1”, brake is asserted when the Brake Pin, P1.1, has the same polarity as
PWMCON2.6. When brake is asserted in response to this pin, the PWMRUN bit in PWMCON1.7 is
automatically cleared, and BKF (PWMCON4.0) flag will be set. When both BKCH and BPEN are “1”,
BKF will be set when Brake pin is asserted, but PWM generator continues to run. With this special
condition, the PWM output does not follow PWMnB, instead it output continuously as per normal
without affected by the brake.
Since the Brake Pin being asserted will automatically clear the PWMRUN (PWMCON1.7) and BKF
(PWMCON4.0) flag will be set, the user program can poll this bit or enable PWM’s brake interrupt to
determine when the Brake Pin causes a brake to occur. The other method for detecting a brake
caused by the Brake Pin would be to tie the Brake Pin to one of the external interrupt pins. This latter
approach is needed if the Brake signal is of insufficient length to ensure that it can be captured by a
polling routine. When, after being asserted, the condition causing the brake is removed, the PWM
outputs go to whatever state that had immediately prior to the brake. This means that in order to go
from brake being asserted to having the PWM run without going through an indeterminate state, care
must be taken. If the Brake Pin causes brake to be asserted, the following prototype code will allow
the PWM to go from brake to run smoothly by software polling BKF flag or enable PWM’s interrupt.
Rewrite PWMCON2 to change from Brake Pin enabled to S/W Brake.
Write PWM (0, 2, 4, 6) Compare register to always “1”, FFFh, or always “0”, 000h, to initialize PWM
output to a High or Low, respectively.
Clear BKF flag.
Set PWMCON1 to enable PWMRUN and Load.
Poll Brake Pin until it is no longer active.
Poll PWMCON1 to find that Load Bit PWMCON1.6 is “0”. When “0”:
Write PWMP (0, 2, 4, and 6) Counter register for desired pulse widths and counter reload values.
Set PWMCON1 to Run and Transfer.
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