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參數(shù)資料
| 型號(hào)： | W79E227APG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | ROHS COMPLIANT, PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 147/200頁(yè) |
| 文件大小： | 3644K |
| 代理商： | W79E227APG |
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Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 147 -
Revision A2.0
SYMBOL
DEFINITION
ADDRESS
MSB
BIT_ADDRESS, SYMBOL
LSB
RESET
I2TIMER
I2C Timer Counter
Register
I2C Clock Rate
EFH
-
-
-
-
-
ENTI
DIV4
TIF
xxxx x000B
I2CLK
EEH
I2CLK.7 I2CLK.6 I2CLK.5 I2CLK.4 I2CLK.3 I2CLK.2 I2CLK.1 I2CLK.0 0000 0000B
I2STAT
US.7
US.6
US.5
US.4
US.3
I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0 0000 0000B
ADDR.7 ADDR.6 ADDR.5 ADDR.4 ADDR.3 ADDR.2 ADDR.1 GC
-
ENS
STA
STO
SI
I2CSAD
EN.7
EN.6
EN.5
EN.4
EN.3
I2STATUS I2C Status Register
EDH
I2STAT
I2STAT
I2STAT
I2STAT
-
-
-
1111 1000B
I2DAT
I2ADDR
I2CON
I2CSADEN Address
I2C Data
I2C Slave Address
I2C Control Register
ECH
EAH
E9H
0000 0000B
x000 000xB
AA
I2CSAD
EN.2
I2CIN
I2CSAD
EN.1
-
I2CSAD
EN.0
F6H
I2CSAD
I2CSAD
I2CSAD
I2CSAD
1111 1110B
Table 17-1: Control Registers of I2C Ports
17.2.1 Slave Address Registers, I2ADDR
I2C port is equipped with one slave address register. The contents of the register are irrelevant when
I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the
MCU’s own slave address. The I2C hardware will react if the contents of I2ADDR are matched with
the received slave address.
The I2C ports support the “General Call” function. If the GC bit is set the I2C port1 hardware will
respond to General Call address (00H). Clear GC bit to disable general call function.
When GC bit is set, the device is in slave mode which can receive the General Call address(00H) sent
by Master on the I2C bus. This special slave mode is referred to as GC mode.
17.2.2 Data Register, I2DAT
This register contains a byte of serial data to be transmitted or a byte which has just been received.
The CPU can read from or write to this 8-bit directly addressable SFR while it is not in the process of
shifting a byte. Data in I2DAT remains stable as long as SI is set. The MSB is shifted out first.While
data is being shifted out, data on the bus is simultaneously being shifted in; I2DAT always contains the
last data byte present on the bus. Thus, in the event of arbitration lost, the transition from master
transmitter to slave receiver is made with the correct data in I2DAT.
I2DAT and the acknowledge bit form a 9-bit shift register which shifts in or out an 8-bit byte, followed
by an acknowledge bit. The acknowledge bit is controlled by the hardware and cannot be accessed by
the CPU. Serial data is shifted into I2DAT on the rising edges of serial clock pulses on the SCL line.
When a byte has been shifted into I2DAT, the serial data is available in I2DAT, and the acknowledge
bit (ACK or NACK) is returned by the control logic during the ninth clock pulse. Serial data is shifted
out from I2DAT on the falling edges of SCL clock pulses, and is shifted into I2DAT on the rising edges
of SCL clock pulses.
I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0
shifting direction
I2C Data Register:
Figure 17-2: I2C Data Shift
17.2.3 Control Register, I2CON
The CPU can read from and write to this 8-bit, directly addressable SFR
.
Two bits are affected by
hardware: the SI bit is set when the I2C hardware requests a serial interrupt, and the STO bit is
cleared when a STOP condition is present on the bus. The STO bit is also cleared when ENS = "0".
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