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參數(shù)資料
| 型號(hào)： | W79E227APG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | ROHS COMPLIANT, PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 149/200頁(yè) |
| 文件大小： | 3644K |
| 代理商： | W79E227APG |
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Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 149 -
Revision A2.0
17.2.7 I2C Maskable Slave Address
This register enables the Automatic Address Recognition feature of the I2C. When a bit in the
I2CSADEN is set to 1, the same bit location in I2CSADDR1 will be compared with the incoming serial
port data. When I2CSADEN.n is 0, then the bit becomes a don't-care in the comparison. This register
enables the Automatic Address Recognition feature of the I2C. When all the bits of I2CSADEN are 0,
interrupt will occur for any incoming address.
1
0
Fosc
1/4
14-bits Counter
TIF
Clear Counter
ENTI
SI
DIV4
ENS1
To I2C Interrupt
Enable
SI
Figure 17-3: I2C Time-out Block Diagram
17.3 Modes of Operation
The on-chip I2C ports support five operation modes, Master transmitter, Master receiver, Slave
transmitter, Slave receiver, and GC cal
l
.
In a given application, I2C port may operate as a master or
as a slave. In the slave mode, the I2C port
hardware looks for its own slave address and the general call address. If one of these addresses is
detected, and if the slave is willing to receive or transmit data from/to master(by setting the AA bit),
acknowledge pulse will be transmitted out on the 9
th
clock, hence an interrupt is requested on both
master and slave devices if interrupt is enabled. When the microcontroller wishes to become the bus
master, the hardware waits until the bus is free before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost in the master mode, I2C port switches to the
slave mode immediately and can detect its own slave address in the same serial transfer.
17.3.1 Master Transmitter Mode
Serial data output through SDA while SCL outputs the serial clock. The first byte transmitted contains
the slave address of the receiving device (7 bits) and the data direction bit. In this case the data
direction bit (R/W) will be logic 0, and we say that a “W” is transmitted. Thus the first byte transmitted
is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge
bit is received. START and STOP conditions are output to indicate the beginning and the end of a
serial transfer.
17.3.2 Master Receiver Mode
In this case the data direction bit (R/W) will be logic 1, and we say that an “R” is transmitted. Thus the
first byte transmitted is SLA+R. Serial data is received via SDA while SCL outputs the serial clock.
Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit is transmitted.
START and STOP conditions are output to indicate the beginning and end of a serial transfer.
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