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參數(shù)資料
| 型號： | W79E804 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 63/115頁 |
| 文件大小： | 1456K |
| 代理商： | W79E804 |
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W79E804A/803A/802A
Publication Release Date: July 16, 2007
- 63 -
Revision A2
Continued
SOURCE
FLAG
VECTOR
ADDRESS
INTERRUPT
ENABLE
BITS
INTERRUPT
PRIORITY
FLAG
CLEARED BY
ARBITRATION
RANKING
POWER
DOWN
WAKEUP
Timer 0
Interrupt
TF0
000BH
ET0 (IE.1)
IP0H.1,
IP0.1
Hardware,
software
4
No
I2C Interrupt
SI
0033H
EI2 (EIE.0)
IP1H.0,
IP1.0
Software
5
No
External
Interrupt 1
IE1
0013H
EX1 (IE.2)
IP0H.2,
IP0.2
Hardware,
Follow the
inverse of
pin
6
Yes
KBI Interrupt
KBF
003BH
EKB
(EIE.1)
IP1H.1,
IP1.1
Software
7
Yes
Comparator
1 Interrupt
CMF
1
0063H
EC1
(EIE.2)
IP1H.2,
IP1.2
Software
8
Yes
Timer 1
Interrupt
TF1
001BH
ET1 (IE.3)
IP0H.3,
IP0.3
Hardware,
software
9
No
Comparator
2 Interrupt
CMF2 0043H
EC2
(EIE.3)
IP1H.3,
IP1.3
Software
10
Yes
Serial Port
Tx and Rx
TI &
RI
0023H
ES (IE.4)
IP0H.4,
IP0.4
Software
11
No
PWM
Interrupt
BKF
0073H
EPWM
(EIE.5)
IP1H.5,
IP1.5
Software
12 (lowest)
No
Note:
1. The Watchdog Timer can wake up Power Down Mode when its clock source is from internal RC.
Table
12-3: Vector location for Interrupt sources and power down wakeup
12.3 Response Time
The response time for each interrupt source depends on several factors, such as the nature of the
interrupt and the instruction underway. In the case of external interrupts
INT0
and
INT1
, they are
sampled at C3 of every machine cycle and then their corresponding interrupt flags IEx will be set or
reset. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has
occurred. These flag values are polled only in the next machine cycle. If a request is active and all
three conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes
four machine cycles to be completed. Thus there is a minimum time of five machine cycles between
the interrupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the
instruction being executed, then an additional delay is introduced. The maximum response time (if no
other interrupt is in service) occurs if the W79E804 series are performing a write to IE, EIE, IP0, IP0H,
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