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參數資料
| 型號： | W79E804 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 79/115頁 |
| 文件大小： | 1456K |
| 代理商： | W79E804 |
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W79E804A/803A/802A
Publication Release Date: July 16, 2007
- 79 -
Revision A2
SM0
SM1
MODE
TYPE
BAUD CLOCK
FRAME
SIZE
START
BIT
STOP
BIT
9TH BIT
FUNCTION
0
0
0
Synch.
4 or 12 TCLKS
8 bits
No
No
None
0
1
1
Asynch.
Timer 1
10 bits
1
1
None
1
0
2
Asynch.
32 or 64 TCLKS
11 bits
1
1
0, 1
1
1
3
Asynch.
Timer 1
11 bits
1
1
0, 1
Table
16-5: Serial Port Mode Summary Table
16.5 Framing Error Detection
A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data
communication. Typically the frame error is due to noise and contention on the serial communication
line. The W79E804 series have the facility to detect such framing errors and set a flag which can be
checked by software.
The Frame Error FE bit is located in SCON.7. This bit is normally used as SM0 in the standard 8051
family. However, in the W79E804 series it serves a dual function and is called SM0/FE. There are
actually two separate flags, one for SM0 and the other for FE. The flag that is actually accessed as
SCON.7 is determined by SMOD0 (PCON.6) bit. When SMOD0 is set to 1, then the FE flag is
indicated in SM0/FE. When SMOD0 is set to 0, then the SM0 flag is indicated in SM0/FE.
The FE bit is set to 1 by hardware but must be cleared by software. Note that SMOD0 must be 1 while
reading or writing to FE. If FE is set, then any following frames received without any error will not clear
the FE flag. The clearing has to be done by software.
16.6 Multiprocessor Communications
Multiprocessor communications makes use of the 9th data bit in modes 2 and 3. In the W79E804
series, the RI flag is set only if the received byte corresponds to the Given or Broadcast address. This
hardware feature eliminates the software overhead required in checking every received address, and
greatly simplifies the software programmer task.
In the multiprocessor communication mode, the address bytes are distinguished from the data bytes
by transmitting the address with the 9th bit set high. When the master processor wants to transmit a
block of data to one of the slaves, it first sends out the address of the targeted slave (or slaves). All the
slave processors should have their SM2 bit set high when waiting for an address byte. This ensures
that they will be interrupted only by the reception of an address byte. The Automatic address
recognition feature ensures that only the addressed slave will be interrupted. The address comparison
is done in hardware not software.
The addressed slave clears the SM2 bit, thereby clearing the way to receive data bytes. With SM2 = 0,
the slave will be interrupted on the reception of every single complete frame of data. The unaddressed
slaves will be unaffected, as they will be still waiting for their address. In Mode 1, the 9th bit is the stop
bit, which is 1 in case of a valid frame. If SM2 is 1, then RI is set only if a valid frame is received and
the received byte matches the Given or Broadcast address.
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