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參數資料
型號: W83194R-67A
廠商: WINBOND ELECTRONICS CORP
元件分類: XO, clock
英文描述: 100MHZ 3-DIMM CLOCK FOR VIA MVP4
中文描述: 124 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: SSOP-48
文件頁數: 11/18頁
文件大小: 237K
代理商: W83194R-67A
W83194R-67A
PRELIMINARY
Publication Release Date: Feb. 1999
- 11 - Revision 0.30
9.0 SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused
inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
Symbol
Parameter
Rating
Vdd , V
IN
Voltage on any pin with respect to GND
- 0.5 V to + 7.0 V
T
STG
Storage Temperature
- 65
°
C to + 150
°
C
T
B
Ambient Temperature
- 55
°
C to + 125
°
C
T
A
Operating Temperature
0
°
C to + 70
°
C
9.2 AC CHARACTERISTICS
Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V , VddL1 =VddL2= 2.5V
, T
A
= 0 C to +70 C
Parameter
Symbol
Min
Output Duty Cycle
CPU/SDRAM to PCI Offset
t
OFF
Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM)
CPU/SDRAM
Cycle to Cycle Jitter
CPU/SDRAM
Absolute Jitter
Jitter Spectrum 20 dB
Bandwidth from Center
Output Rise (0.4V ~ 2.0V)
& Fall (2.0V ~0.4V) Time
t
THL
Overshoot/Undershoot
Beyond Power Rails
Ring Back Exclusion
V
RBE
Typ
50
Max
55
4
Units
%
ns
Test Conditions
Measured at 1.5V
15 pF Load Measured at 1.5V
45
1
t
SKEW
250
ps
15 pF Load Measured at 1.5V
t
CCJ
ó
250
ps
t
JA
500
ps
BW
J
500
KHz
t
TLH
0.4
1.6
ns
15 pF Load on CPU and PCI
outputs
V
over
1.5
V
22
at source of 8 inch PCB
run to 15 pF load
2.1
V
Ring Back must not enter this
range.
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PDF描述
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相關代理商/技術參數
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