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參數(shù)資料
| 型號： | W83759A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ADVANCED VL-IDE DISK CONTROLLER |
| 中文描述： | 先進(jìn)的VL - IDE磁盤控制器 |
| 文件頁數(shù)： | 9/41頁 |
| 文件大小： | 334K |
| 代理商： | W83759A |
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W83759A
Publication Release Date: May 1995
- 9 -
Revision A1
Pin Description, continued
SYMBOL
PIN
TYPE
DESCRIPTION
SP1
/IDEA0
67
I/O
-PD
When
SYSRST
is active, this pin is an input that latches on the
rising edge of
SYSRST
.
SP1: VL-Bus speed select. A high input configures the W83759A
to run at from 33 MHz to 50 MHz; a low input configures the
W83759A to run at under 33 MHz.
IDEA0: IDE drive address bit 0. Drive address bit 0 is output to
the IDE connector for register selection in the drive.
IDD[15:0]
72
87
I/O
-PU
When
SYSRST
is active, these pins function as inputs and latch
on the rising edge of
SYSRST
.
As power-on setting pins, IDD[15:8] are latched to the POSS3
register and IDD[7:0] are latched to the POSS2 register.
As the drive data bus, bits 15 through 0 are the 16-bit bidirectional
data bus that connects to the IDE drive.
IDD[7:0] define the lowest data byte. The IDD bus is normally in a
pull-high state and is driven with valid data by the W83759A only
during IDE or VGA (
VGAOEH
= 0 or
VGAOEL
= 0) write cycles.
ISA-Bus Interface
SA[1:0]
47, 46
I
ISA address bits 1 and 0.
Used to select the hard disk I/O registers.
SD[7:0]
58-51
I/O
These signals provide data bus bits 0 through 7 for the CPU and
IDE I/O devices. SD0 is the least significant bit and SD7 is the
most significant bit.
XIOR
48
I
XIOR
instructs the hard disk I/O device to drive its data onto the
SD data bus.
XIOW
49
I
XIOW
instructs the hard disk I/O device to read the data on the
SD data bus.
AEN
50
I
When this line is active (high), the DMA controller has control of
the address bus. A low is the address enable.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W83768 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:I/O COUPLER |
| W83769 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LOCAL BUS IDE SOLUTION |
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