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參數資料
| 型號： | W83769 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | LOCAL BUS IDE SOLUTION |
| 中文描述： | 局部總線IDE解決方案 |
| 文件頁數： | 15/21頁 |
| 文件大小： | 163K |
| 代理商： | W83769 |
W83769
Publication Release Date: September 1994
- 15 -
Revision A1
2. SIGNAL DESCRIPTION
NAME
NO.
TYPE
DESCRIPTION
CLOCK AND RESET
CLKIN
89
I
Input clock to the W83769. This clock has the same
frequency as the local bus clock.
RESET
IDEACT
88
I
Reset pin from local bus to reset the chip.
87
I
Chip enable pin. When set high, the W83769 is enabled
after reset. When set low, the W83769 is disabled.
HOST INTERFACE
FRAME
12
I
FRAME is driven by the current master to indicate the
beginning and duration of an access. While FRAME is
asserted, data transaction continues. When FRAME is de-
asserted, the transaction is in the final data phase.
IRDY
13
I
IRDY indicates the PCI bus master can complete the
current data phase of the transaction.
TRDY
14
B
TRDY indicates the PCI bus slave can complete the current
data phase of the transaction.
DEVSEL
17
O
The W83769 drives this signal active to indicate that it has
decoded its address as the target of the current access.
STOP
18
B
STOP indicates the W83769 is requesting that the current
master stop the current transaction.
IDSEL
1
I
IDSEL is asserted by PCI system to select the W83769
during configuration read and write transactions.
PAR
20
B
The W83769 drives PAR in read data phases for parity
checking.
HIRQ
79
O
IRQ14 output to the system chip set.
CBE0
3
31, 21,
11, 100
I
These inputs are the multiplexed Bus Command and Byte
Enable signals on the PCI bus.
IRQL
85
I
The IRQL pin controls the polarity of the HIRQ output. When
this pin is tied high, the polarity of HIRQ will follow that of
DIRQ (pin 50). When this pin is tied low, the polarity of
HIRQ will be the reverse of that of DIRQ.
PERR
19
B
The PERR pin reports data parity errors during data read
phases.
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