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參數資料
| 型號： | W83C553F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | SYSTEM I/O CONTROLLER WITH PCI ARBITER |
| 中文描述： | ISA BUS CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, PLASTIC, QFP-208 |
| 文件頁數： | 53/159頁 |
| 文件大小： | 3984K |
| 代理商： | W83C553F |
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W83C553F
3.21 82C54 Counter/Timer
One 82C54 counter/timer, with three channels, is included in the W83C553F. The clocks for the three channels are
connected to the 14.31818 MHz clock through a divide-by-twelve counter. The gate inputs of counters 0 and 1 are tied high
so that they are always enabled. The gate input of counter 2 is tied to bit 0 of Port B, inside the chip. The output of counter 0
is connected to the IRQ0 input of the interrupt controllers. The output of counter 1 goes to the arbitration logic for a refresh
request. Finally, the output of counter 2 goes to an AND gate, which drives the SPKR output pin. The other input to this
AND gate comes from bit 1 of Port B.
3.22 PCI Arbiter
The W83C553F contains a programmable, eight master PCI arbiter which can be tailored to meet system-specific arbitration
requirements. Pin 16 is available to strap the arbiter into its disabled state on power-up. A weak 2.2K ohm pull-down
resistor is recommended for this in systems using an external arbiter. When disabled, the "Function 0" ISA bridge uses the
REQ#/GNT# pair on pins 25 and 26, and the "Function 1" IDE uses the REQ#/GNT# pair on pins 27 and 28. If no pull-
down resistor is used on pin 16, the on-chip arbiter will "come up" enabled after power up.
When in the active state, the eight masters supported by the W83C553F are its two internal masters (ISA bridge and IDE),
the system CPU, and REQ#/GNT#[4:0] which are available to the system designer. The PCI5TH# function of pin 13 can be
used to change the fifth REQ#/GNT# pair (on pins 6 and 7) to FLSHREQ#/FLSHACK# if desired (in either CPU mode).
This PCI5TH# function is automatically overidden by the ARBDIS# pin when enabled.
FLSHREQ#/FLSHACK# are only used in Guaranteed Access Timing (GAT) mode. In GAT mode, before Function 0 makes
a request for the PCI bus, it asserts FLSHREQ# to the system and waits for FLSHACK# to be asserted. The system can use
this signal to flush all PCI buffers so that the W83C553F can be granted unimpeded access to main memory. When Function
0 (PCI-to-ISA bridge) is not in GAT mode, it behaves as any other PCI master device.
Upon power-up, the arbiter defaults to a "round-robin" rotation scheme allowing all PCI masters equal access to the local bus.
If desired, the relative priority of each REQ/GNT pair can be custom tailored to a specific system design via the PCI Priority
Control Register 1 at Index 80h in the Function 0 PCI Configuration Space. Note that all masters are assured of access to the
PCI bus at least once during each rotation regardless of the programming options chosen. (This is required for PCI
compliance, so no functions are "locked out" for an extended period).
Electrical Specifications
WINBOND SYSTEMS LABORATORY
50
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相關代理商/技術參數 |
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|---|---|
| W83C553FG | 制造商:Winbond Electronics Corp 功能描述: |
| W83C553F-G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:W83C553F-G Highly Integrated System I/O Controller for Power PCTM (South Bridge) QFP 208 |
| W83C553FY-G | 制造商:Nuvoton Technology Corp 功能描述:I/O Controller Phase Controller 208-Pin PQFP 制造商:Winbond Electronics 功能描述:I/O CONTROLLER 制造商:Nuvoton Technology 功能描述:I/O Controller Phase Controller 208-Pin PQFP |
| W83C554F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:SYSTEM I/O CONTROLLER WITH PCI ARBITER & UltraDMA/33 IDE Controller |
| W83C554FY | 制造商:Nuvoton Technology Corp 功能描述:I/O Controller Phase Controller 制造商:Nuvoton Technology 功能描述:I/O Controller Phase Controller |
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