
W921E840A/W921C840
- 14 -
6.2.1 Special Control Register Map, continued
ADDR.
02CH
02DH
02EH
02FH
030H
031H
032H
033H
034H
035H
036H
037H
038H
039H
03AH
03BH
03CH
03DH
03EH
03FH
DESCRIPTION
ABBREVIATION
(TM2LSB)
(STTM2)
(TGTM2)
(TM3CR)
(TM3MSB)
(TM3LSB)
(STTM3)
(ENINT)
(STPRF)
(HMRF1)
(HMRF2)
(HMRF3)
(INTCT1)
(INTCT2)
(INTCT3)
(HRSTS1)
(HRSTS2)
(HRSTS3)
(BTGR)
INITIAL VALUE
0FH
00H
00H
00H
0FH
0FH
00H
-
00H
08H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
TM2 LSB Data Register
TM2 Status Register
TM2 Trigger Condition Register
TM3 Control Register
TM3 MSB Data Register
TM3 LSB Data Register
TM3 Status Register
Reserved
Interrupt Enable Flag
Stop Mode Released Flag
Hold Mode Released Flag 1
Hold Mode Released Flag 2
Hold Mode Released Flag 3
Interrupt Control Register 1
Interrupt Control Register 2
Interrupt Control Register 3
Hold Released Status Flag 1
Hold Released Status Flag 2
Hold Released Status Flag 3
Beep Tone Generator Register
6.2.2 Stack Register Area
A 8-bit stack pointer indicates the stack located address from 040H to 0FFH. After power on reset the
stack pointer will be set to 0FFH. The stack pointer will be decreased by 4 when the CALL/ CALLP or
interrupt is accepted, and will be increased by 4 when the RTN or RTNI instruction is executed. The
format of the stack content is shown in the following table.
0FFH
0FEH
0FDH
0FCH
0FBH
0FAH
0F9H
0F8H
Stack 0
Stack 1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
Z
C
PC0
PC12
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
Z
C
PC12