
W921E840A/W921C840
Publication Release Date: July 1999
- 21 - Revision A3
PA, PB, PC, PD:
PABCDPH register: (address = 007H, default data = 0H)
b3
b2
b1
b0
0:
1:
0:
1:
0:
1:
0:
1:
PA (4 pins) without pull-high resistor
PA (4 pins) with pull-high resistor
PB (4 pins) without pull-high resistor
PB (4 pins) with pull-high resistor
PC (3 pins) without pull-high resistor
PC (3 pins) with pull-high resistor
PD (2 pins) without pull-high resistor
PD (2 pins) with pull-high resistor
PABCDTP register: (address = 008H, default data = 0H)
b3
b2
b1
b0
0:
1:
0:
1:
0:
1:
0:
1:
PA (4 pins) work as CMOS type
PA (4 pins) work as open-drain type
PB (4 pins) work as CMOS type
PB (4 pins) work as open-drain type
PC (3 pins) work as CMOS type
PC (3 pins) work as open-drain type
PD (2 pins) work as CMOS type
PD (2 pins) work as open-drain type
P2:
P2TP register: (address = 00DH, default data = 0H)
b3
b2
b1
b0
0:
1:
P2 (4 pins) work as CMOS type
P2 (4 pins) work as open-drain type
Reserved
Reserved
0:
1:
PC.3 works as normal I/O port (CMOS type)
PC.3 works as 32.768KHz output buffer
(open-drain type) only for W921E841A,
843A, 844A
6.6 Serial Port
The W921E840A/W921C840 has a clock-synchronous serial interface which transmits and receives
8-bit data as default. User can program the P6IO register to select port P6 as the serial port. The
serial transmitter/receiver function can be operated with multi-nibble function and the LSB of every
nibble is transmitted/received first.
The serial transmitted/received data are come from or are stored into the serial buffer registers
(address 050H to 14EH); how many nibbles will be transmitted/received is decided by the serial MSB
nibble register (SRMNR, address = 00AH) and serial LSB nibble register (SRLNR, address = 009H).