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參數資料
型號: W93910
廠商: WINBOND ELECTRONICS CORP
元件分類: 尋呼電路
英文描述: ERMES(Enhanced Radio Emessage System) Paging Protcol Decoder(增強的無線電子信息系統尋呼解碼器)
中文描述: TELECOM, PAGING DECODER, PDSO28
封裝: SSOP-28
文件頁數: 15/35頁
文件大小: 267K
代理商: W93910
W93910
Publication Release Date: Auguest 1999
- 15 - Revision A1
LOST SYNCHCONIZATION
If synchronization is lost for several minutes (pre-defined by option bit LKR1
LKR0 ), the pager will
change to the channel scan mode. The
SYNVAL
pin will keep low during the lock mode and normal
mode unless the synchronization lost duration exceeds the hold time condition, then the
SYNVAL
pin
will change to high level and the decoder will go back to the channel scan mode.
OPTION BIT
FUNCTION
LKR1
LKR0
Synchronization lost hold time
0
0
1 min.
0
1
2 min.
1
0
3 min.
1
1
4 min.
Table 9. Lock re-try option bits
RIC (Radio Identify Code) FORMAT
For ERMES system, RIC has 35 bits and is defined by ZC2
ZC0, CC6
CC0, OP2
OP0, IA17
IA0, and
BN3
BN0 option bits as shown in Table 10.
Radio Identify Code
Function
OPID
LOCAL ADDRESS
Zone Code Country Code Operator Code Initial Address Batch Number Paging area
OPTION
ZC2
ZC0
CC6
CC0
OP2
OP0
IA17
IA0
GIA17
GIA0
BN3
BN0
PA5
PA0
GPA5
GPA0
bit
Table 10. RIC format
The W93910 provides two initial addresses with corresponding paging area code, IA17
IA0 with
PA5
PA0 and GIA17
GIA0 with GPA5
GPA0, for the same OPID. The first one is dedicated for the
basic RIC. Each pager has one unique batch number, defined by BN3
BN0, and will only turn on and
listen at that specific batch except where a message continues over one batch. If PAEN option bit is set
to "1", the received message must match to the pre--defined paging area code, PA5
PA0. Other than in
this situation, the received paging area code doesn't need to match the pre-defined PA5
PA0, but must
be consistent throughout the whole message. The second IA, GIA17
GIA0, is enabled by setting the
GIAEN option bit to 1. GPAEN has the same function as PAEN, but for GIA17
GIA0 address only.
OPTION BIT
FUNCTION
GIAEN
Second user address (GPA+GIA)
0
Disable
1
Enable
Table 11-1. Second initial address setting option bits
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