
W986408AH
2M x 8 bit x 4 Banks SDRAM
Revision 1.2 Publication Release Date: May, 1998
- 21 -
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)
(CLK = 100 MHz)
CLK
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
BS0
tRC
tRC
tRC
tRAS
tRP
tRAS
tRP
tRAS
tRAS
tRP
tRCD
tRCD
tRCD
tRCD
tAC
tAC
tAC
tAC
tRRD
tRRD
tRRD
tRRD
Active
Read
Active
Read
Active
Active
Active
Read
Read
tRC
RAa
RBb
RAc
RBd
RAe
DQ
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
cy0
cy1
cy2
cy3
dz0
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
AP*
AP*
RAa
CAw
RBb
CBx
RAc
CAy
RBd
RAe
CBz