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參數資料
| 型號： | W986416CH-7 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | x16 SDRAM |
| 中文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數： | 5/48頁 |
| 文件大小： | 1647K |
| 代理商： | W986416CH-7 |
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W986416DH
Publication Release Date: April 11, 2002
- 5 -
Revision A4
5. PIN DESCRIPTION
PIN NUMBER PIN NAME
FUNCTION
DESCRIPTION
23
26, 22,
29
35
A0
A11 Address
Multiplexed pins for row and column address.
Row address: A0
A11. Column address: A0
A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
20, 21
BS0, BS1 Bank Select
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
DQ0
DQ15
Data Input/
Output
Multiplexed pins for data output and input.
19
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
18
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of
the clock RAS, CAS and WE define the
operation to be executed.
17
CAS
Column
Address Strobe
Referred to RAS
16
WE
Write Enable
Referred to RAS
39, 15
UDQM
LDQM
Input/output
Mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
38
CLK
Clock Inputs
System clock used to sample inputs on the rising edge
of clock.
37
CKE
Clock Enable CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
1, 14, 27
V
CC
Power (+3.3V)
Power for input buffers and logic circuit inside DRAM.
28, 41, 54
V
SS
Ground
Ground for input buffers and logic circuit inside DRAM.
3, 9, 43, 49
V
CCQ
Power (+3.3V)
for I/O Buffer
Separated power from V
CC
, to improve DQ noise
immunity.
6, 12, 46, 52
V
SSQ
Ground for I/O
Buffer
Separated ground from V
SS
, to improve DQ noise
immunity.
36, 40
NC
No Connection
No connection
相關PDF資料 |
PDF描述 |
|---|---|
| W986416CH-75 | x16 SDRAM |
| W986416CH-8H | x16 SDRAM |
| W986432DH | 512K ⅴ 4 BANKS ⅴ 32 BITS SDRAM |
| W986432AH | 512K x 4 BANKS x 32 BITS SDRAM |
| W986432AH-55 | x32 SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W986416CH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x16 SDRAM |
| W986416CH-8H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x16 SDRAM |
| W986416DH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M X 4 BANKS X 16 BITS SDRAM |
| W986416DH-5 | 制造商:Winbond Electronics Corp 功能描述:4M X 16 SYNCHRONOUS DRAM, 4.5 ns, 54 Pin Plastic SMT |
| W986416DH-55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X1MX16|CMOS|TSOP|54PIN|PLASTIC |
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