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參數(shù)資料
| 型號(hào)： | W9925QF-K |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | A High Performance Single-Chip VCD Decoder(高性能的單片VCD解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大小： | 177K |
| 代理商： | W9925QF-K |
Preliminary
W9925QF-K
Publication Release Date: April, 1998
Revision 1.0
- 10 -
MONO
Output one key-shifted data on both channels, according to the setting of bit(1).
CH
Select the source channel to be output in mono mode, if MONO=0 this bit will be ignored.
KC_ON
Indicates key-shift function is ON or OFF, 1=ON; 0=OFF (no up/down control)
Karaoke Memory Slot Register
index: FDh
write
bit(15:11)
not used
bit(10:0)
slot size
Karaoke Memory Fragment Register
index: FEh
write
bit(15:11)
not used
bit(10:0)
fragment size
These two registers are used to set the slot size of PCM buffer in DRAM. This is used when the
available DRAM space for PCM buffer is not continuous. The Karaoke control will allocate PCM
buffer address according to these two registers with start/end address.
8.9 DM RAM Parameters
Most of the DM RAM initialization is same as BB/B, in addition, the following parameters should be pre-set before
W9925QF-K start A/V decoding.
DM initialization
Parameter
PCMSEL
M2LR
Address
7D1h
7E5h
Type
W
W
Content
pcm path select, 1:from KC 0:from DSP
Mono audio duplicated to L/R channel
1:enable
0:disable
1: decode layer2 brate 192/224 only 0:decode all type
of bitstream
must set 0
Set 0x4000;
Set 0xFFFF;
Set 0x4000;
Set 0x4000;
Set 0x92E4;
Set 0x5a33;
L+R mixed mode gain control (0.5)
Set 0
VCDL2
7E6h
W
reserved
3DSP0
3DSP1
3DSP2
3DSP3
3DSP4
3DSP5
LPRGC
DUMSKP
7E7h
7E8h
7E9h
7EAh
7EBh
7ECh
7EDh
7EEh
7EFh
W
W
W
W
W
W
W
W
W
PCMSEL
PCM path selection, host set 1 to enable the Key Control and set 0 or CD-DA/MPEG decoding
.
M2LR
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