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參數資料
型號: WHT9361
廠商: WINBOND ELECTRONICS CORP
元件分類: 衰減器
英文描述: 902-928MHZ GFSK RF Module(902-928MHZ的GFSK式調制/解調的射頻模塊)
中文描述: RF/MICROWAVE UP/DOWN CONVERTER
封裝: 16 PIN
文件頁數: 3/12頁
文件大小: 98K
代理商: WHT9361
Preliminary WHT9361
Publication Release Date: August 1998
- 3 -
Revision A1
B) Receiver
From the antenna port, the RF signal passes through the ceramic bandpass filter to remove signals
outside the 902
928 MHz band, then routes through the T/R switch and enters the low noise amplifier
(LNA). After signal amplification, the signal is down-converted to IF signal and filtered by a high
selective SAW filter to reject out-band spurious signals and interference. Before going to the
Discriminator Demodulator, the IF signal is processed by a limiting amplifier with a gain over 70 dB
to improve the noise performance. It finally passes through the LPF and Comparator to get the raw
data information. The Receiving Signal Strength Indicator (RSSI) comes out of the limiter, which can
be used as a power control reference for the baseband microprocessor (
μ
P).
C) VCO & Synthesizer
A single frequency synthesizer IC with voltage controlled oscillator (VCO) is used to generate the
transmission and receiving frequency channels. Channel selection is done by programming the
control register in the synthesizer IC through the serial interface bus using the microcontroller. The
PLL specification and related information is described in a later section.
SPECIFICATIONS OF RF MODULE
Frequency Band:
Channel Spacing:
Selectable Channel Numbers:
Non-overlapping channels:
Frequency Stability
Phase Noise:
902 to 928 MHz
2.048 MHz (minimum)
over 70 channels
10 (with the W9310F SST chip)
±
50 ppm (depends on input reference clock)
-90dBc/Hz @100 KHz (depends on input reference
clock)
< 500
μ
S
1.365 Mbps
20
±
2 dBm/high power (with BATT_IN >= 3.6V )
2 steps, 15
±
2 dB difference between High and
Low output power
PLL Lock Up Time:
Transmission Chip Rate:
Power Output:
Power Control:
Modulation:
Dynamic Range:
Received Signal Strength Indication:
Spurious Emission:
Current Consumption
T/R Access:
T/R Time Frame/Time Slot:
BT = 0.5 GFSK
-30 to -90 dBm @ BER <10 E-3 (typically)
0.5
2.3 VDC
FCC part 15 compliance
270 mA/TX (typical)
70 mA/RX (typical)
TDD
9.0 mS/ 4.5 mS
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