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參數資料
| 型號： | WHT9361 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 衰減器 |
| 英文描述： | 902-928MHZ GFSK RF Module(902-928MHZ的GFSK式調制/解調的射頻模塊) |
| 中文描述： | RF/MICROWAVE UP/DOWN CONVERTER |
| 封裝： | 16 PIN |
| 文件頁數： | 8/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | WHT9361 |
Preliminary WHT9361
- 8 -
RF MODULE & SST CHIP INTERFACE TIMING CHART
RF Module interfaces with the W9310F SST chip through the following pins: DEMOD_DATA,
MOD_DATA, PLL_SW, and RF_PWR. PLL_SW and RF_PWR are used to switch on/off receiver and
to power on/off the transmitter power amplifier respectively. The timing diagram for the PLL_SW and
RF_PWR when it is used with W9310F SST chip for operation in two-way (full-duplex)
communication mode is shown in Figure 4. The timing assumes that there is no air propagation delay
between master and slave. However, when operated in half-duplex communication mode, the
PLL_SW and RF_PWR are always ON (High) when the Module is set as Master (Transmitter) and
OFF (Low) when it is set as Slave mode.
0
767
0
TRANSMIT_MASTER
FRAME TIMING
408
754
19
365
-8
370
760
20
370
BSYNC
259
RECEIVER_MASTER
PLL_CLK
PLL_DATA
PLL_LE
TRANSMIT_SLAVE
RECEIVE_SLAVE
-9
409
759
-9
381
759
408
754
787
19
-9
MOD_DATA
PLL_SW
RF_PWR
DEMOD_OUT
RF_PWR
DEMOD_OUT
MOD_DATA
PLL_SW
Figure 4. The FRAME timing diagram of W9310F and PLL programming
Notes:
1. The timing is expressed as numbers of bits.
2. The total number of bits per burst is fixed and equal for both the master and slave.
3. The total Time Frame is 768 bits long.
4. 1-bit duration = 11.7
μ
S.
5. Refer to W9310F data sheet for detailed Frame timing information.
6. Receiver synthesizer data is sent in previous transmittng frame. Then this data is loaded and enabled at the beginning of
receiving frame; viceversa for the transmitter.
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