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參數資料
| 型號： | WHT9361 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 衰減器 |
| 英文描述： | 902-928MHZ GFSK RF Module(902-928MHZ的GFSK式調制/解調的射頻模塊) |
| 中文描述： | RF/MICROWAVE UP/DOWN CONVERTER |
| 封裝： | 16 PIN |
| 文件頁數： | 4/12頁 |
| 文件大小： | 98K |
| 代理商： | WHT9361 |
Preliminary WHT9361
- 4 -
MECHANICAL & ENVIRONMENTAL
Operating Temperature:
Storage Temperature:
Module Dimensions:
45 mm
×
60 mm
×
10 mm (including shield case)
0
°
C to +50
°
C
-30
°
C to +70
°
C
RECOMMENDED ANTENNA SPECIFICATION
Frequency Range:
Frequency Center:
Gain:
VSWR:
890 to 940 MHz
915 MHz
2 dBi
2:1
RF-BASEBAND INTERFACE DESCRIPTIONS & PIN ASSIGNMENTS
The RF Module interface defined herein is the interface to the baseband portion; it uses a 16-pin male
connector (refer to appendix A). The only other interface of the RF Module is the antenna port which
uses a 2-pin male connector (refer to appendix A). The pin-assignment and descriptions of the RF-to-
BASEBAND interface are described below; the pin-allocation diagram is shown in Appendix B:
NO.
PIN NAME
TYPE
DESCRIPTION
1
BATT_IN
Input
DC power supply input (max 4.8V) to provide the DC power
for the power amplifiers.
Current consumption: < 230 mA max. @ 3.6V
2
16.384 MHz
Input
Input as the reference source of the synthesizer.
Frequency stability:
±
50 ppm
Phase noise: < -110 dBc @
±
5 KHz
Grounding
3
GND
4*
PLL_DATA
Input
Serial data input to the divider in the synthesizer to set the
operation channel. CMOS Level.
5 *
PLL_CLK
Input
Clock input to synthesizer. CMOS Level.
6*
PLL_LE
Input
Rising edge trigger. When LE is HIGH or OPEN, data stored
in the shift register is loaded to the appropriate latch. CMOS
Level.
7
DEMOD_DATA
Output
Demodulated data output to DSP (SST chip). CMOS Level.
8**
RF_PWR
Input
Transmitter on
(HIGH) and off (LOW) control. CMOS Level.
9
VCC_REG
Output
Regulated V
CC
output (3.0 VDC)
10
MOD_DATA
Input
Data input from DSP (SST chip). As it affects the RF Module
transmitter modulation index, the HIGH Level output needs to
be fixed at 3
±
0.2V.
HIGH input: 3
±
0.2V
LOW input: 0V
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