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參數(shù)資料
型號(hào)： TLC320AD80CPM
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, TQFP-64
文件頁數(shù)： 20/37頁
文件大小： 229K
代理商： TLC320AD80CPM
3–5
3.4
Timing Requirements, TA = 25 °C, AVDD = DVDD = 5 V ± 5%, fs = 48 kHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input frequency,
MCLK1, MCLK2
4.096
18.432
MHz
fs
Audio sample rate
8
48
kHz
tsu1
Setup time, PCM data
Relative to the rising edge of BCLK
60
ns
th1
Hold time, PCM data
Relative to the rising edge of BCLK
0
ns
tsu2
Setup time, LRCLK
Relative to the rising edge of BCLK
60
ns
th2
Hold time, LRCLK
Relative to the rising edge of BCLK
0
ns
3.4.1
Serial PCM Data Port (see Figures 3–1 and 3–2)
PARAMETER
MIN
TYP
MAX
UNITS
tc(BCLK)
Cycle time, BCLK
60
ns
tr(BCLK)
Rise time, BCLK
0
ns
tf(BCLK)
Fall time, BCLK
0
ns
tsu(LRCLK)
Setup time, LRCLK
↓ before BCLK↑
0
ns
th(LRCLK)
Hold time, LRCLK
↑ after BCLK↑
0
ns
tsu(SDATA)
Setup time, SDATA before BCLK
↑
0
ns
th(SDATA)
Hold time, SDATA after BCLK
↑
0
ns
td(SDATA)
Delay time, SDATA valid after BCLK
↓
0
ns
twL(BCLK)
Pulse duration, BCLK low
60
ns
twH(BCLK)
Pulse duration, BCLK high
60
ns
twL(MCLK)
Pulse duration, MCLK low
60
ns
twH(MCLK)
Pulse duration, MCLK high
60
ns
tr(MCLK)
Rise time, MCLK
0
ns
tf(MCLK)
Fall time, MCLK
0
ns
3.4.2
Serial Control Interface, TA = 25°C, AVDD = DVDD = 5 V ± 5%, (see Figure 3–3)
DESCRIPTION
MIN
TYP
MAX
UNITS
fSCLK
Input frequency, SCLK
3
MHz
tc(SCLK)
Cycle time, SCLK
333
ns
twL(SCLK)
Pulse width, SCLK low
100
ns
twH(SCLK)
Pulse width, SCLK high
100
ns
tsu(CS)
Setup time, CS
↓ before SCLK↓
150
ns
th(CS)
Hold time, CS
↑ after SCLK↑
150
ns
tsu(CDIN)
Setup time, CDIN before SCLK
↑
50
ns
th(CDIN)
Hold time, CDIN after SCLK
↑
50
ns
td(CDOUT)
Delay time, CDOUT after SCLK
↓
30
ns
th(CDOUT)
Hold time, CDOUT after SCLK
↓
5
ns
tr(SCLK)
Rise time, SCLK
100
ns
tf(SCLK)
Fall time, SCLK
100
ns
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參數(shù)描述
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