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參數(shù)資料
| 型號： | TLC320AD80CPM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 6/37頁 |
| 文件大小： | 229K |
| 代理商： | TLC320AD80CPM |
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2–3
2.1.1.1
Main Serial PCM Port
The main serial PCM (SDATA, BCLK, and LRCLK) port always operates in slave mode. That is, all clocks
are inputs to the device. The LRCLK and BCLK clocks must be synchronous with MCLK.
A typical set-top-box application would connect this input to an MPEG/AC3 audio decoder.
2.1.1.2
Aux Serial PCM Data Port
The aux serial port (ASDATA, ABCLK, and ALRCLK) operates in either the master or slave mode. The
master mode supports all the documented interface protocols with the exception of the DSP mode. The
slave mode supports all documented protocols without exception.
The aux serial PCM data port receives non-compressed data from an auxillary audio source. The slave
mode is identical to the clock mode of main serial PCM port. In the master mode, this device generates the
required BCLK and LRCLK clocks synchronously with the applied MCLK.
2.1.1.3
Serial Interface Protocols Supported
The serial ports comprise the signals in Table 2–1.
Table 2–1. Serial Port Signals
MAIN PORT
AUXILIARY PORT
DESCRIPTION
SDATA
ASDATA
PCM audio data. 16-bit or 18-bit data precision
BCLK
ABCLK
Bit clock. Rate is equal to 32x, 48x, or 64x the sample rate
LRCLK
ALRCLK
Left/right clock. Rate is equal to the sample rate
Figure 2–1 through Figure 2–4 are for a bit clock (BCLK) set to 48
the sample rate and 16-bit data
precision. All serial protocols supported are shown.
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
16
17
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
16
17
Left Channel
Right Channel
LRCLK
BCLK
SDATA
16 Bit
SDATA
18 Bit
XX X
X X X XX X X X
XX X
X XX X X X
XX X X X X
Figure 2–1. Philips I2S Protocol Serial PCM Data Format
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
16
17
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
16
17
Left Channel
Right Channel
LRCLK
BCLK
SDATA
16 Bit
SDATA
18 Bit
XX
XXXXXXXX
XXXXXXXX X
XX
XXXXXX
XXXXXX X
Figure 2–2. Left-Justified Serial PCM Data Format
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