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參數(shù)資料
| 型號(hào)： | U632H16SK25G1 |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 NON-VOLATILE SRAM, 25 ns, PDSO28 |
| 封裝： | 0.300 INCH, GREEN, SOP-28 |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大小： | 229K |
| 代理商： | U632H16SK25G1 |
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4
April 7, 2005
U632H16
DC Characteristics
Symbol
Conditions
C-Type
K-Type
Unit
Min.
Max.
Min.
Max.
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
2.4
0.4
2.4
0.4
V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
8
-4
8
-4
mA
Input Leakage Current
High
Low
IIH
IIL
VCC
VIH
VIL
= 5.5 V
=
0 V
-1
1
-1
1
A
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VCC
VOH
VOL
= 5.5 V
=
0 V
-1
1
-1
1
A
SRAM Memory Operations
No.
Switching Characteristics
Read Cycle
Symbol
25
35
45
Unit
Alt.
IEC
Min. Max. Min. Max. Min. Max.
1
Read Cycle Timef
tAVAV
tcR
25
35
45
ns
2
Address Access Time to Data Validg
tAVQV
ta(A)
25
35
45
ns
3
Chip Enable Access Time to Data Valid
tELQV
ta(E)
25
35
45
ns
4
Output Enable Access Time to Data Valid
tGLQV
ta(G)
12
20
25
ns
5E HIGH to Output in High-Zh
tEHQZ
tdis(E)
13
17
20
ns
6G HIGH to Output in High-Zh
tGHQZ
tdis(G)
13
17
20
ns
7E LOW to Output in Low-Z
tELQX
ten(E)
55
5
ns
8G LOW to Output in Low-Z
tGLQX
ten(G)
00
0
ns
9
Output Hold Time after Address Change
tAXQX
tv(A)
33
3
ns
10 Chip Enable to Power Activee
tELICCH
tPU
00
0
ns
11 Chip Disable to Power Standbyd, e
tEHICCL
tPD
25
35
45
ns
e: Parameter guaranteed but not tested.
f:
Device is continuously selected with E and G both LOW.
g: Address valid prior to or coincident with E transition LOW.
h: Measured
± 200 mV from steady state output voltage.
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