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參數(shù)資料
| 型號： | U632H16SK25G1 |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 NON-VOLATILE SRAM, 25 ns, PDSO28 |
| 封裝： | 0.300 INCH, GREEN, SOP-28 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大小： | 229K |
| 代理商： | U632H16SK25G1 |
9
April 7, 2005
U632H16
u: If the chip enable pulse width is less then ta(E) (see READ cycle) but greater than or equal to tw(E)SR, then the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U632H16 performs a STORE
or RECALL.
w: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
Ai
E
DQi
Output
tcR
tw(E)SR
High Impedance
ADDRESS 1
VALID
Software Controlled STORE/RECALL Cyclet, u, v, w (E = HIGH after STORE initiation)
ADDRESS 6
(29)
th(A)SR
(35)
(34)
tsu(A)SR
(33)
Ai
E
DQi
Output
tcR
tw(E)SR
High Impedance
ADDRESS 1
VALID
ADDRESS 6
td(E)S (31)
(32)
(29)
th(A)SR
(35)
(34)
tsu(A)SR (33)
tdis(E)SR (30)
th(A)SR (35)
tsu(A)SR
(33)
tw(E)SR
th(A)SR
(35)
(34)
tsu(A)SR
(33)
(5)
tdis(E)
Software Controlled STORE/RECALL Cyclet, u, v, w (E = LOW after STORE initiation)
tdis(E)SR (30)
td(E)S(31)
(32)
td(E)R
tcR
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