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參數資料
型號: W77E58F-25
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 8 BIT MICROCONTROLLER
中文描述: 8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數: 50/85頁
文件大?。?/td> 570K
代理商: W77E58F-25
Preliminary W77E58
- 50 -
Table 6. SFR Reset Value, continued
SFR Name
SCON
SBUF
P2
SADDR1
SCON1
ROMMAP
EXIF
P4
Reset Value
00000000b
xxxxxxxx
b
11111111b
00000000b
00000000b
01
xxx
110b
0000
xxx
0b
xxxx
1111b
SFR Name
B
EIP
PC
SADEN1
SBUF1
PMR
STATUS
Reset Value
00000000b
xxx00000b
00000000b
00000000b
xxxxxxxx
b
010xx0x0b
000x0000b
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset.
External reset
Watchdog reset
WDCON
0x0x0xx0b
0x0x01x0b
Power on reset
01000000b
The POR bit WDCON.6 is set only by the power on reset. The PFI bit WDCON.4 is set when the
power fail condition occurs. However, a power-on reset will clear this bit. The WTRF bit WDCON.2 is
set when the Watchdog timer causes a reset. A power on reset will also clear this bit. The EWT bit
WDCON.1 is cleared by power on resets. This disables the Watchdog timer resets. A watchdog or
external reset does not affect the EWT bit.
INTERRUPTS
The W77E58 has a two priority level interrupt structure with 12 interrupt sources. Each of the interrupt
sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts
can be globally enabled or disabled.
Interrupt Sources
The External Interrupts INT0 and
INT1
can be either edge triggered or level triggered, depending on
bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine
cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected
and the interrupts request flag IEx in TCON or EXIF is set. The flag bit requests the interrupt. Since
the external interrupts are sampled every machine cycle, they have to be held high or low for at least
one complete machine cycle. The IEx flag is automatically cleared when the service routine is called.
If the level triggered mode is selected, then the requesting source has to hold the pin low till the
interrupt is serviced. The IEx flag will not be cleared by the hardware on entering the service routine.
If the interrupt continues to be held low even after the service routine is completed, then the
processor may acknowledge another interrupt request from the same source. Note that the external
interrupts INT2 to INT5 are edge triggered only. By default, the individual interrupt flag corresponding
to external interrupt 2 to 5 must be cleared manually by software. It can be configured with hardware
cleared by setting the corresponding bit HCx in the T2MOD register. For instance, if HC2 is set
hardware will clear IE2 flag after program enters the interrupt 2 service routine.
相關PDF資料
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W77I058A25DL 功能描述:IC MCU 8-BIT 32K FLASH 40-DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:W77 標準包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI,I²C,UART/USART 外圍設備:POR,PWM,WDT 輸入/輸出數:40 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數據轉換器:A/D 8x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC(J 形引線) 包裝:帶卷 (TR)