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參數資料
型號: W77E58F-25
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 8 BIT MICROCONTROLLER
中文描述: 8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數: 70/85頁
文件大小: 570K
代理商: W77E58F-25
Preliminary W77E58
- 70 -
The following example shows how the user can define the Given Address to address different slaves.
Slave 1:
SADDR1010 0100
SADEN1111 1010
Given
1010 0x0x
Slave 2:
SADDR1010 0111
SADEN1111 1001
Given
1010 0xx1
The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don't care, while for slave 2
it is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010
0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate
only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master
wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit
1 = 0. The bit 3 position is don't care for both the slaves. This allows two different addresses to select
both slaves (1010 0001 and 1010 0101).
The master can communicate with all the slaves simultaneously with the Broadcast Address. This
address is formed from the logical ORing of the SADDR and SADEN SFRs. The zeros in the result
are defined as don't cares In most cases the Broadcast Address is FFh. In the previous case, the
Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2.
The SADDR and SADEN SFRs are located at address A9h and B9h respectively. On reset, these two
SFRs are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXX
XXXX(i.e. all bits don't care). This effectively removes the multiprocessor communications feature,
since any selectivity is disabled.
TIMED ACCESS PROTECTION
The W77E58 has several new features, like the Watchdog timer, on-chip ROM size adjustment, wait
state control signal and Power on/fail reset flag, which are crucial to proper operation of the system. If
left unprotected, errant code may write to the Watchdog control bits resulting in incorrect operation
and loss of control. In order to prevent this, the W77E58 has a protection scheme which controls the
write access to critical bits. This protection scheme is done using a timed access.
In this method, the bits which are to be protected have a timed write enable window. A write is
successful only if this window is active, otherwise the write will be discarded. This write enable
window is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this
window automatically closes. The window is opened by writing AAh and immediately 55h to the Timed
Access(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed
access window is
TA
REG
0C7h
;define new register TA, located at 0C7h
MOV
TA, #0AAh
MOV
TA, #055h
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W77I058A25DL 功能描述:IC MCU 8-BIT 32K FLASH 40-DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:W77 標準包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI,I²C,UART/USART 外圍設備:POR,PWM,WDT 輸入/輸出數:40 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數據轉換器:A/D 8x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC(J 形引線) 包裝:帶卷 (TR)