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參數(shù)資料
| 型號(hào)： | W77L32 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 17/74頁 |
| 文件大小： | 871K |
| 代理商： | W77L32 |
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Preliminary W77L32
Publication Release Date: November 2, 2001
- 17 - Revision A1
XT/RGRG: Crystal/RC Oscillator Select. Setting this bit selects crystal or external clock as system
clock source. Clearing this bit selects the on-chip RC oscillator as clock source.
XTUP(STATUS.4) must be set to 1 and XTOFF (PMR.3) must be cleared before this bit
can be set. Attempts to set this bit without obeying these conditions will be ignored. This
bit is set to 1 after a power-on reset and unchanged by other forms of reset.
RGMD: RC Mode Status. This bit indicates the current clock source of microcontroller. When cleared,
CPU is operating from the external crystal or oscillator. When set, CPU is operating from the
on-chip RC oscillator. This bit is cleared to 0 after a power-on reset and unchanged by other
forms of reset.
RGSL: RC Oscillator Select. This bit selects the clock source following a resume from Power Down
Mode. Setting this bit allows device operating from RC oscillator when a resume from Power
Down Mode. When this bit is cleared, the device will hold operation until the crystal oscillator
has warmed-up following a resume from Power Down Mode. This bit is cleared to 0 after a
power-on reset and unchanged by other forms of reset.
Serial Port Control
Bit:
7
6
5
4
3
2
1
TI
0
RI
SM0/FE
SM1
SM2
REN
TB8
RB8
Mnemonic: SCON
Address: 98h
SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines
whether this bit acts as SM0 or as FE. The operation of SM0 is described below. When used
as FE, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in
software to clear the FE condition.
SM1:
Serial port Mode bit 1:
SM0 SM1 Mode
Description
0
0
0
Synchronous
0
1
1
Asynchronous 10
1
0
2
Asynchronous 11
1
1
3
Asynchronous 11
Length
8
Baud rate
4/12 Tclk
variable
64/32 Tclk
variable
SM2:
Multiple processors communication. Setting this bit to 1 enables the multiprocessor
communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI will not be
activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will not be
activated if a valid stop bit was not received. In mode 0, the SM2 bit controls the serial port
clock. If set to 0, then the serial port runs at a divide by 12 clock of the oscillator. This gives
compatibility with the standard 8052. When set to 1, the serial clock become divide by 4 of the
oscillator clock. This results in faster synchronous serial communication.
Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled.
This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software as
desired.
In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the stop bit
that was received. In mode 0 it has no function.
Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
at the beginning of the stop bit in all other modes during serial transmission. This bit must be
cleared by software.
REN:
TB8:
RB8:
TI:
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