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參數(shù)資料
| 型號： | W77L32 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 57/74頁 |
| 文件大小： | 871K |
| 代理商： | W77L32 |
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Preliminary W77L32
Publication Release Date: November 2, 2001
- 57 - Revision A1
executed now, then the reset watchdog timer instructions will not be executed at the required instants
and watchdog reset will occur.
The watchdog time-out selection will result in different time-out values depending on the clock speed.
The reset, when enabled, will occur 512 clocks after the time-out has occurred.
Table 9. Time-out values for the Watchdog timer
WD1
WD0
WATCHDOGIN
TERVAL
2
17
2
20
2
23
2
26
NUMBER OF
CLOCKS
131072
1048576
8388608
67108864
TIME
@1.8432 MHz
71.11 mS
568.89 mS
4551.11 mS
36408.88 mS
TIME
@10 MHz
13.11 mS
104.86 mS
838.86 mS
6710.89 mS
TIME
@25 MHz
5.24 mS
41.94 mS
335.54 mS
2684.35 mS
0
0
1
1
0
1
0
1
The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not
disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into a
known state.
The control bits that support the Watchdog timer are discussed below.
WATCHDOG CONTROL
WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the
watchdog timer. If the Watchdog interrupt is enabled (EIE.4), then an interrupt will occur (if the
global interrupt enable is set and other interrupt requirements are met). Software or any reset
can clear this bit.
WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.
This bit is useful for determined the cause of a reset. Software must read it, and clear it
manually. A Power-fail reset will clear this bit. If EWT = 0, then this bit will not be affected by
the watchdog timer.
EWT: WDCON.1 - Enable Watchdog timer Reset. This bit when set to 1 will enable the Watchdog
imer reset function. Setting this bit to 0 will disable the Watchdog timer reset function, but will
leave the timer running
RWT: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog timer and to restart
it. This bit is self-clearing, so after the software writes 1 to it the hardware will automatically
clear it. If the Watchdog timer reset is enabled, then the RWT has to be set by the user within
512 clocks of the time-out. If this is not done then a Watchdog timer reset will occur.
CLOCK CONTROL
WD1, WD0: CKCON.7, CKCON.6 - Watchdog Timer Mode select bits. These two bits select the time-
out interval for the watchdog timer. The reset time is 512 clock longer than the interrupt
time-out value.
The default Watchdog time-out is 2
17
clocks, which is the shortest time-out period. The EWT, WDIF
and RWT bits are protected by the Timed Access procedure. This prevents software from accidentally
enabling or disabling the watchdog timer. More importantly, it makes it highly improbable that errant
code can enable or disable the watchdog timer.
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