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參數資料
| 型號： | W77L32 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 45/74頁 |
| 文件大小： | 871K |
| 代理商： | W77L32 |
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Preliminary W77L32
Publication Release Date: November 2, 2001
- 45 - Revision A1
instead of crystal to exit Power Down mode. The microcontroller will automatically switch from RC
oscillator to crystal after clock is stable. The RC oscillator runs at approximately 2
4 MHz. Using RC
oscillator to exit from Power Down mode saves the time for waiting crystal start-up. It is useful in the
low power system which usually be awakened from a short operation then returns to Power Down
mode.
Table 5. Status of external pins during Idle and Power Down
MODE
PROGRAM
MEMORY
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
10. RESET CONDITIONS
The user has several hardware related options for placing the W77L32 into reset condition. In general,
most register bits go to their reset value irrespective of the reset condition, but there are a few flags
whose state depends on the source of reset. The user can use these flags to determine the cause of
reset using software. There are ways of putting the device into reset state, external reset and watchdog
reset.
External Reset
The device continuously samples the RST pin at state C4 of every machine cycle. Therefore the RST
pin must be held for at least 2 machine cycles to ensure detection of a valid RST high. The reset
circuitry then synchronously applies the internal reset signal. Thus the reset is a synchronous operation
and requires the clock to be running to cause an external reset.
Once the device is in reset condition, it will remain so as long as RST is 1. Even after RST is
deactivated, the device will continue to be in reset state for up to two machine cycles, and then begin
program execution from 0000h. There is no flag associated with the external reset condition. However
since the other two reset sources have flags, the external reset can be considered as the default reset
if those two flags are cleared.
Watchdog Timer Reset
The Watchdog timer is a free running timer with programmable time-out intervals. The user can clear
the watchdog timer at any time, causing it to restart the count. When the time-out interval is reached an
interrupt flag is set. If the Watchdog reset is enabled and the watchdog timer is not cleared, then 512
clocks from the flag being set, the watchdog timer will generate a reset . This places the device into the
reset condition. The reset condition is maintained by hardware for two machine cycles. Once the reset
is removed the device will begin execution from 0000h.
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